Extracting wiring parasitics for filtered interconnections in an integrated circuit

Abstract

A method (200), system (100) and computer program product for extracting parasitic resistance and capacitance values to simulate performance values to simulate performance of an integrated circuit. A selected number of interconnections in an integrated circuit may be identified (204) ('interconnections of interest'). A netlist containing a list of the transistors in the integrated circuit may be pruned by selecting those transistors in the netlist that are in the channel connected regions on the driving side of the interconnections of interest and those on the receiving side of the interconnections of interest (205, 206). Parasitic resistance and capacitance values for layout layers connected to the interconnections of interest may be extracted (208). These extracted parasitic resistance and capacitance values may be associated with the transistors connected to those layout layers in the pruned netlist (209). By extracting parasitic resistance and capacitance values as describe above, less compute-intensive RC extractions may be made thereby using less memory and processing power.

Description

technical field [0001] The present invention relates to the field of electronic design automation, and more particularly to a method and system for extracting parasitic resistance and capacitance of selected interconnections in an integrated circuit using less memory and processing power than the prior art. Background technique [0002] The field commonly referred to as Electronic Design Automation (EDA) has evolved to handle the demanding and complex design of semiconductor integrated circuits. EDA means the use of computers to design and simulate the performance of electronic circuits on integrated circuits, commonly referred to as "chips." Computers are well suited for performing the tasks associated with designing programs because they can be programmed to reduce, or break down, large and complex circuits into simpler functional units. [0003] After the circuitry of a semiconductor chip has been designed and physically laid out, the operation of the integrated circuit ...

AI Technical Summary

Problems solved by technology

While these EDA vendors may have developed software tools that perform RC extractions more accurately, these software tools require computationally intensive RC extractions for each interconnect, requiring significant amounts of memory and processing power

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