Semiconductor device

Abstract

The invention provides a semiconductor device, which is characterized by including a substrate with an electrode section; a first semiconductor component, which has a first electrode solder pad connected on the electrode section by a first bonding lead, and is adhered onto the substrate; and a second semiconductor component, which has a second electrode solder pad connected on the electrode section by a second bonding lead, and is adhered onto the first semiconductor component by an adhesive agent layer which has a two-layer structured formed by the same material and having different elastic rates.

Description

technical field [0001] The present invention relates to a semiconductor device in which a plurality of semiconductor elements are stacked. Background technique [0002] In recent years, a stacked multi-chip package in which a plurality of semiconductor elements (semiconductor chips) are stacked and packaged in a single package has been put into practical use in order to achieve miniaturization and high-density packaging of semiconductor devices. In such a stacked multi-chip package, a plurality of semiconductor elements are sequentially stacked on a mounting substrate such as a circuit board through an adhesive such as a die-bonding material, and the electrodes of each semiconductor element are electrically connected by bonding wires. Electrode parts such as pads and circuit boards. In addition, by encapsulating such a laminated structure with a sealing resin, a laminated multi-chip package is constituted. [0003] However, in the stacked multi-chip package described above...

AI Technical Summary

Problems solved by technology

[0017] As described above, in semiconductor devices using the conventional stacked multi-chip package structure, poor insulation or short circuits due to contact between the bonding wires of the semiconductor element on the lower side and the semiconductor element on the upper side have occurred. Main factors hindering the thinning of packages

In addition, although the insulating layer provided on the lower surface side of the semiconductor element on the upper stage side is effective in suppressing the above-mentioned poor insulation or short circuit, etc., it causes a layer caused by a difference in thermal expansion coefficient between the insulating layer and the adhesive layer. stripping or increase in manufacturing costs, etc.

Furthermore, in a stacked structure in which a hollow portion is formed below the semiconductor element on the upper side, cracks in the semiconductor element or bonding wires of the semiconductor element on the lower side may occur due to deflection that occurs during wire bonding of the semiconductor element on the upper side. deformation, poor connection, etc.

[0018] In addition, in conventional semiconductor devices with a stacked multi-chip package structure, when semiconductor elements larger than those on the lower side are stacked on the upper side, or semiconductor elements on the upper side are stacked with an offset, the upper side A part of the semiconductor element protrudes from the semiconductor element on the lower side, and the lower part of the protruding part is inevitably formed in a hollow state

If the lower part of the protruding part is formed in a hollow state, there will be problems such as poor connection of the bonding wire connected to the semiconductor element on the upper stage, or cracks on the semiconductor element on the upper stage due to bending during wire bonding.

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