Standard cell, semiconductor integrated circuit device of standard cell scheme and layout design method for semiconductor integrated circuit device

Abstract

The invention prevents the potential inversion of the dynamic nodes due to the fact that any connection between standard cells made on the same level as the wiring layer of the dynamic nodes inside the standard cells is arranged to be the same as Dynamic nodes are adjacent. Near the dynamic node 101 inside the standard cell, shielded wirings 102a and 102b made of wiring layers at the same level as the dynamic node are provided, thereby preventing any wiring between standard cells from passing adjacent to the dynamic node. The shielded wiring can be replaced by a shielded area or a wiring keepout area.

Description

technical field

[0001] The invention relates to a standard cell, a semiconductor integrated circuit device of the standard cell scheme, and a layout design method for the semiconductor integrated circuit device. Background technique

[0002] The standard cell scheme is one of techniques used to design large scale integration (LSI). In the standard cell scheme, a desired circuit is constructed by preparing in advance various small-scale circuits called "standard cells" and then combining them. In the layout design of an LSI for a standard cell scheme, automatic placement and wiring to which a software tool is applied is performed. In the layout design of the automatic placement and routing scheme, various circuits of different functions are constructed in a short time by arranging standard cells on a semiconductor substrate and performing wiring between standard cells according to specifications.

[0003] In an LSI based on automatic placement and routing of the prior art, ...

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