Semiconductor memory device

Abstract

The present invention relates to a one-bit memory cell MC that consists of an MOS transistor that is provided with a floating area that is electrically isolated from other parts. A grid 13 of the MOS transistor is connected with a word line WL; a drain diffusion area 14 is connected with a bit line BL; a source diffusion area 15 is connected with a fixed potential line SL; a first threshold state of a plurality of carriers that are injected into the body area 12 of the MOS transistor and are generated by impact ionization, and a second threshold state of a plurality of carriers of the body area 12 of the MOS transistor, which are released as a result of positive bias of the drain side pn junction, perform as binary data for storage. Therefore, a simple transistor is used as a memory cell; and the present invention can provide a semiconductor memory device that has fewer signal lines and can dynamically store the binary data.

Description

[0001] This application is a divisional application of an invention patent application filed by Toshiba Corporation on August 17, 2001, with the application number 01145060.6 and the title of the invention "semiconductor storage device and its manufacturing method". technical field [0002] The present invention relates to a dynamic semiconductor memory device (DRAM). Background technique [0003] The existing DRAM is a storage unit composed of MOS transistors and capacitors. The miniaturization of DRAM has greatly advanced with the adoption of a trench capacitor structure or a multilayer capacitor structure. Now, assuming that the minimum processing size rule is F, the size (unit size) of the unit storage unit is reduced to 2F*4F=8F 2 area. That is, the minimum processing size rule F decreases with the replacement, and the unit size is generally set as αF 2 , the coefficient α also decreases with the replacement, and now F=0.18μm, α=8 can be realized. [0004] In the fu...

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Problems solved by technology

[0014] However, (1) the structure is complicated, and it is difficult to control the characteristics due to the use of parasitic transistors

(2) Although the structure is simple, the source and drain of the transistor need to be connected to the signal line to control the potential

In addition, due to well isolation, the cell size is large, and each bit cannot be rewritten

As for (3), it is necessary to control the potential from the side of the SOI substrate, so it is not possible to rewrite every bit, and there are difficulties in controllability

(4) The structure of special transistors needs to be made. In addition, word lines, write bit lines, read bit lines and buses need to be made on the memory cells, and the number of signal lines increases.

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