Semiconductor device and method for forming semiconductor device
A technology of semiconductors and conductors, applied in the field of semiconductor devices, can solve problems such as electric field changes, large changes in the slope of the sub-threshold, and changes in the slope of the sub-threshold, and achieve small temperature sensitivity, fast switching, and precise effects
Inactive Publication Date: 2006-06-07
TAIWAN SEMICON MFG CO LTD
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This results in large variations in the electric field in the offset channel region 34 during switching, which in turn results in large changes in the sub-threshold slope
In addition, the breakdown mechanism of existing gated PIN diodes is temperature sensitive, so that temperature changes will also cause sub-threshold slope changes
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[0036] In order to make the above objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.
[0037] The process steps of the embodiments of the present invention will be disclosed, and variations of the preferred embodiments will be presented. In the illustrated embodiment of the invention as well as in the different drawings, the same reference numerals are used to designate the same elements. Each figure number has the letter A, B, or C to indicate a variation of the same procedural step.
[0038] Figure 3A to Figure 10 A gated PIN diode according to an embodiment of the present invention will be described. Figure 3A It is illustrated that a shallow trench isolation (STI) 52 is formed on the substrate 50 . The STI 52 is preferably formed by etching a shallow trench in the substrate 50 and filling the trench with an insulator such as silicon oxide. In ...
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The invention provides a semiconductor device and a method for forming the semiconductor device, in particular to a gate control PIN diode and a method for forming the same. The gated PIN diode includes a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source gate interval and a drain gate interval along the disposed along respective sides of the gate dielectric layer and the gate; a source, doped with a dopant of a first type, substantially below the source-gate spacer, and connected to a first of the gate a horizontal distance between the sides; a drain doped with a second-type dopant extending substantially below the drain-gate spacer and substantially vertically aligned with a second side of the gate , wherein the first type is opposite to the second type; a source silicide is adjacent to the source; and a drain silicide is adjacent to the drain. The formation of the offset region of the present invention is more precise, so that the accumulative collapse mechanism is better controlled.
Description
technical field [0001] The present invention relates to a semiconductor device, in particular to a PIN diode. Background technique [0002] In integrated circuits of 90nm technology, metal-oxide-semiconductor (MOS) is an important technology. According to the gate voltage V g vs. source-drain voltage V ds , a MOS device can operate in three regions, namely the linear region, the subthreshold region, and the saturation region. In the sub-threshold region, the gate voltage V g less than the threshold voltage V t . The sub-threshold slope indicates the ease with which the transistor current is turned off, and thus becomes an important factor in determining the speed of a MOS device. The sub-threshold slope can be represented by the formula m×kT / q, where m is a parameter related to capacitance. The sub-threshold slope of a typical MOS device has a limit of approximately 60mV / decade (kT / q), and then sets a limit to scale the operating voltages Vcc and V t . This limitati...
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IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/7391H01L29/868
Inventor 陈宏玮李文钦柯志欣季明华葛崇祜
Owner TAIWAN SEMICON MFG CO LTD