Quickflashing memory unit manufacturing method

A storage unit and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as influence, poor quality of gate oxide layer, and limitation of surface cleaning steps

Inactive Publication Date: 2006-07-12
MACRONIX INT CO LTD
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  • Abstract
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Problems solved by technology

Therefore, the traditional process can produce many adverse effects on the oxide / nitride / oxide (ONO) gate dielectric layer
[0006] Furthermore, in order to prevent the loss of the oxide / nitride / oxide (ONO) gate dielectric layer, the surface cleaning step before the formation of the gate oxide layer in the peripheral region is usually significantly restricted, so that the gate oxide layer in the peripheral region Quality is also adversely affected

Method used

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  • Quickflashing memory unit manufacturing method
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  • Quickflashing memory unit manufacturing method

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Embodiment Construction

[0015] The method of the present invention will be described in detail according to the following preferred embodiment and with reference to the accompanying drawings.

[0016] A preferred embodiment of the invention is shown in Figure 1A to Figure 1D and Figure 2A to Figure 2E ,in Figure 1A to Figure 1D It is a schematic cross-sectional view of various formation steps of the peripheral region (periphery region) of the flash electrically erasable and programmable read-only memory unit of the present invention, and Figure 2A to Figure 2E It is a schematic cross-sectional view of various formation steps of the memory cell region of the flash electrically erasable and programmable read-only memory unit of the present invention.

[0017] refer to Figure 1A and Figure 2A , a tunnel oxide layer 101 is formed on a semiconductor substrate 100 with a first conductivity. The semiconductor substrate 100 can be an N-type or P-type substrate, preferably a P-type silicon substrate....

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Abstract

The manufacture method for a fast flash memory unit comprises: after forming an oxide/nitride/oxide (ONO) dielectric layer on a first conductive layer of a cross-tunnel oxide layer, forming a second conductive layer on the ONO layer; then, figured etching the second layer to form a peripheral area on an exposed surface of substrate and a memory unit area on residual second conductive layer. Wherein, the ONO layer is protected by said second layer during the process. Thereby, this invention can obtain high-quality ONO grid dielectric layer.

Description

technical field [0001] The invention relates to a method for manufacturing a non-volatile memory unit; in particular, it relates to a method for manufacturing a flash memory unit. Background technique [0002] With the expansion of application fields, such as the development of mobile phones and digital cameras, electrically erasable and programmable read-only memory devices (EEPROM) have been widely used rapidly. EEPROM devices can electrically erase all stored data at the same time, and are called flash EEPROM devices. [0003] Electrically erasable and programmable read-only memory device is a non-volatile memory device that stores digital data according to the specified amount of stored charge, and reads the stored data by changing the conductivity of a channel region. of digital data. [0004] Each memory cell of a traditional flash electrically erasable and programmable read-only memory device is mainly based on a metal oxide semiconductor transistor (MOS transistor)...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247
Inventor 吴俊沛陈辉煌陈鸿祺高瑄苓
Owner MACRONIX INT CO LTD
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