Semiconductor memory device

Abstract

Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line and reduces current consumption in the non-select bit line. The semiconductor memory device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a data line, a plurality of selector circuits, at least one precharge circuit, and at least one pull-down circuit. The selector circuits switch electrical connections and isolations between the respective bit lines and the data line. The precharge circuit precharges the select bit line to a predetermined voltage level which is different from a voltage level of a first voltage line. The pull-down circuit pulls the select bit line down to the voltage level of the first voltage line.

Description

technical field [0001] The present invention relates to a semiconductor storage device such as a mask ROM (Read Only Memory). Background technique [0002] It is widely known as a semiconductor storage device such as a mask ROM. The so-called mask ROM refers to a semiconductor storage device dedicated to reading, in which storage values ​​are written in memory cells at the manufacturing stage. [0003] refer to Figure 14 , the conventional mask ROM readout circuit will be described. [0004] The memory cell array 100 includes a plurality of memory cell transistors T11 to Tmn. Gates of the memory cell transistors T11 to Tmn are connected to word lines WL1 to WLm arranged in the row direction. Drains of the memory cell transistors T11 to Tmn are connected to bit lines BL1 to BLn arranged in the column direction. [0005] The sources of some memory cell transistors are connected to the first power supply line at ground potential (GND level), that is, ...

AI Technical Summary

Problems solved by technology

[0026] However, in the readout circuit of the conventional mask ROM described above, since the transistors connected to the non-selected bit line and the selected word line are turned on due to the low-level readout (ground state) , so the through current flowing between the source and the drain increases the power consumption

In particular, when the number of bit lines is large, since a through current flows through all low-level read memory cell transistors connected to the selected word line, there will be a problem of excessive peak current.

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