Stack architecture of multiple chips

Abstract

The stack frame of multiple chips includes carrier for chips, first chipset, cushion piece, and second chipset. The first chipset possesses multiple chips. Possessing unilateral weld pads, these chips are stacked on carrier for chips in stair shape. The cushion piece is joined to the first chipset. Possessing unilateral weld pads, the first chipset possesses multiple chips. Bottommost chip in the second chipset is joined to the cushion piece in deflection towards direction of weld pads of the first chipset. Then, the second chipset is stacked on carrier in stair shape. Weld pads are revealable in order to prevent stack of chips from exceeding packaging region. The invention encapsulates chips in multiple layers to package without increasing area of package. Being able to be stacked in package, multiple chips does not deviate stack in single direction so as to facilitate throwing for weld part of chip.

Description

technical field [0001] The invention relates to a multi-chip stacking structure, in particular to a stacking structure of a plurality of chips with single-side welding pads. Background technique [0002] Due to the miniaturization of electronic products and the increase in the demand for high-speed operation, in order to improve the performance and capacity of a single semiconductor package structure to meet the needs of miniaturization of electronic products, the multi-chip modularization (Multi chip Module) of the semiconductor package structure has become a The trend is to combine two or more semiconductor chips in a single package structure to reduce the overall circuit volume and improve electrical functions. That is, the multi-chip package structure can minimize the limitation of the system operating speed by combining two or more chips in a single package structure. In addition, the multi-chip package structure can reduce the length of connecting lines between chips,...

AI Technical Summary

Problems solved by technology

[0005] Although the above-mentioned existing multi-chip stacking structure saves space compared with the side-by-side chip method, and can stack the chips first and then perform the wire bonding operation, its biggest disadvantage is that when stacking more layers of chips, the stacking method makes it constantly tilt to one side , so that the projected area of ​​the entire chip stack is bound to increase continuously, such as Figure 1B As shown, assuming that the side length of the semiconductor chip is S, each additional stacked semiconductor chip must be far away from the pad area L of the lower semiconductor chip, so as to facilitate the wire bonding operation, so when n layers of chips are stacked, The stack projection length of the semiconductor chip will be S+(n-1)L; it can be seen that when the chips are continuously stacked in a single direction in a stepwise manner, when the stack reaches a certain number of layers, the chip will exceed the packageable range. At the same time, the chip carrier area of ​​the package must be increased to complete the stacked chip, but increasing the area of ​​the package also affects the area of ​​the overall electronic product, which violates the requirement for small volume and multi-functional characteristics of electronic products

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