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Method and apparatus for forming an soi body-contacted transistor

一种晶体管、电接触的技术,应用在形成SOI体接触晶体管领域,能够解决降低引出效率等问题

Inactive Publication Date: 2007-01-03
FREESCALE SEMICON INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The depleted portion of the extrinsic body-extraction access region causes higher antibody-extraction conditions, resulting in reduced body-extraction efficiency

Method used

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  • Method and apparatus for forming an soi body-contacted transistor
  • Method and apparatus for forming an soi body-contacted transistor
  • Method and apparatus for forming an soi body-contacted transistor

Examples

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Embodiment Construction

[0022] image 3 is a layout of a novel SOI body-contact transistor 80 according to an embodiment of the present invention. The SOI body-contact transistor 80 includes an active transistor region 82 including a portion thereof serving as a body-tie contact region, indicated at 84 . The intrinsic body region, which is near the center of the active transistor region 82, includes a width dimension 86, denoted "W 1 ”, and the length scale 88, denoted as “L 1 ". A portion of the active region, which is near the center of its lead-out region 84, which includes a width dimension 90, denoted "W 2 ”, and the length scale 92, denoted as “L 2 ". This region corresponds to the body-exit access region, and in the image 3 and Figure 4 Indicated by reference numeral 128 .

[0023] SOI body-contact transistor 80 further includes gate polysilicon 94 on active transistor region 82 . The gate polysilicon 94 further includes an access region 128 ( Figure 4 ) corresponds to a portion of th...

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PUM

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Abstract

A method for forming a silicon-on-insulator transistor (80) includes forming an active region (82) overlying an insulating layer (122), wherein a portion of the active region provides an intrinsic body region (126). A body tie access region (128) is also formed within the active region, overlying the insulating layer and laterally disposed adjacent the intrinsic body region, making electrical contact to the intrinsic body region. A gate electrode (134) is formed overlying the intrinsic body region for providing electrical control of the intrinsic body region, the gate electrode extending over a portion (137) of the body tie access region. The gate electrode is formed having a substantially constant gate length (88) along its entire width overlying the intrinsic body region and the body tie access region to minimize parasitic capacitance and gate electrode leakage. First and second current electrodes (98,100) are formed adjacent opposite sides of the intrinsic body region. In addition, a body tie diffusion (130) is formed within the active region and laterally offset from the body tie access region and electrically coupled to the body tie access region.

Description

technical field [0001] The present disclosure relates generally to semiconductor devices, and more particularly, to methods and apparatus for forming SOI body-contact transistors. Background technique [0002] Body-contact SOI transistors are typically constructed with a polysilicon gate that distinguishes the source / drain regions from the body contacts. The additional circuit load capacitance due to this body-tie gate, especially for high-performance technologies that use reticle enhancement techniques such as complementary phase-shift masks to reduce the gate length of the main transistor, is very important. These techniques cannot reduce the size or capacitance of the body-extraction region. [0003] In the prior art, a polysilicon gate is used to separate the source / drain region from the body contact region. This arrangement creates an additional gate capacitance sufficient to increase the gate delay, for example by a factor of 2. Furthermore, although the use of a d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/84H01L21/20H01L21/336H01L27/01H01L29/45H01L29/786
CPCH01L29/458H01L29/78615H01L29/66772H01L27/12H01L21/18
Inventor 苏里亚·维拉拉加万杜洋格伦·O·沃克曼
Owner FREESCALE SEMICON INC
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