Thin film transistor

A thin film transistor, amorphous silicon technology, applied in the direction of transistors, etc., can solve the problems of the thin film transistor 200 not operating normally, the tolerance is insufficient, and the misalignment of the gate 202 and the channel layer 206 is not considered, so as to overcome the errors. Alignment issues, process compatibility, the effect of improved manufacturing yield

Inactive Publication Date: 2007-07-11
IND TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Please refer to FIG. 2B , when the gate 202 and the channel layer 206 are misaligned in the Y-axis direction, the thin film transistor 200 may not operate normally. The main reason is that the layout of the thin film transistor 200 does not take the gate 202 and the channel layer 206, therefore, the tolerance for the misalignment of the gate 202 and the channel layer 206 in the Y-axis direction is obviously insufficient, and further improvement is still needed

Method used

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Examples

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no. 1 example

[0051] FIG. 3A is a schematic layout diagram of a thin film transistor according to a first embodiment of the present invention. Please refer to FIG. 3A, the thin film transistor 300 of this embodiment is suitable for being arranged on a flexible substrate (not shown in the figure), and the thin film transistor 300 includes a gate 302, a gate insulating layer 304, a channel layer 306, a first The conductor pattern 308 and the second conductor pattern 310 . Wherein, the gate 302 is disposed on the flexible substrate, and the gate insulation layer 304 is disposed on the flexible substrate to cover the gate 302 . The channel layer 306 is disposed on the gate insulating layer 304 and above the gate 302 . The channel layer 306 has at least one first contact region 306a and a plurality of second contact regions 306b, and the first contact region 306a is located between the second contact regions 306b. In addition, the first conductive pattern 308 is disposed on a portion of the ga...

no. 2 example

[0059] FIG. 4A is a schematic layout diagram of a thin film transistor according to a second embodiment of the present invention. Please refer to FIG. 4A , the thin film transistor 300a of this embodiment is similar to the thin film transistor 300 of the first embodiment, and both belong to a thin film transistor with a dual source structure. The extension direction of the pole S2 and the drain D. In detail, in the thin film transistor 300 a of this embodiment, the extending direction of the source S1 , the source S2 and the drain D is parallel to the extending direction of the data line DL.

[0060] FIG. 4B is a schematic diagram of misalignment of the thin film transistor of the second embodiment. Please refer to FIG. 4B, when misalignment occurs between the gate 302, the channel layer 306, the first conductor pattern 308, and the second conductor pattern 310 due to the expansion and contraction of the flexible substrate, the source S1 and the drain The channel layer 306 b...

no. 3 example

[0062] FIG. 5A is a schematic layout diagram of a thin film transistor according to a third embodiment of the present invention. Please refer to FIG. 5A, the thin film transistor 300b of this embodiment is similar to the thin film transistor 300a of the second embodiment, but the main difference between the two is: the thin film transistor 300b of this embodiment does not have a source S1, only has a source S2 and Data line DL. In detail, in the thin film transistor 300b of this embodiment, the second conductor pattern 310 includes the source S2 and a data line DL connected to the source S2, and the source S2 and the data line DL respectively cover the corresponding first The second contact area 306b.

[0063] In this embodiment, the extending direction of the source S2 and the drain D is parallel to the extending direction of the data line DL. In addition, the distribution position and quantity of the second contact region 306b in this embodiment are no longer determined by...

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Abstract

This invention relates to one film transistor, which is set on flexible curve baseboard, which comprises grating electrode, grating insulation layer, channel layer, first conductor pattern and second conductor pattern, wherein, the grating electrode is set on baseboard and the insulation layer is set on curve baseboard to cover grating electrode; the channel layer is set on grating insulation layer on grating electrode; the channel layer has at least one first contact area and multiple contact area.

Description

technical field [0001] The present invention relates to a thin film transistor, and in particular to a thin film transistor suitable for being manufactured on a flexible substrate. Background technique [0002] In order to match the modern life style, the volume of video or image devices is becoming thinner and lighter. Although the traditional cathode ray tube (Cathode Ray Tube, CRT) display still has its advantages, due to the structure of its internal electronic cavity, the cathode ray The size of the tube display is bulky and takes up space, and radiation rays are generated while the cathode ray tube display outputs images to damage the eyes. Therefore, flat panel displays (Flat Panel Display, FPD) developed by combining optoelectronic technology and semiconductor manufacturing technology, such as plasma display (Plasma Display Panel, DPD), liquid crystal display (Liquid Crystal Display, LCD), organic electroluminescent display ( Organic Electro-Luminescence Display, OE...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/786
Inventor 赖志明叶永辉黄怡硕
Owner IND TECH RES INST
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