High performance, low power vertical integrated CMOS devices

Abstract

A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETS; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer. The SRAM cell may be radiation hardened by selectively thickening gate layers to increase storage node capacitance, providing high resistance cell wiring or by including a multi-layered gate oxide layer of NO or ONO, or by any combination thereof.

Description

[0001] The present invention is related to U.S. patent application Ser. No. 08 / ______ (Attorney Docket No. BU9-96-123) entitled "High Performance Direct Coupled FET Memory Cell" to Bertin et al., filed coincident herewith and assigned to the assignee of the present application.[0002] 1. Field of the Invention[0003] The present invention is related to integrated circuit (IC) chips and more particularly, to IC chips with CMOS SRAM cells and logic.[0004] 2. Background Description[0005] Integrated circuit (IC) chip developers' primary goals are faster, denser, lower power IC chips. Typical, state of the art IC chips are manufactured, currently, in the complementary insulated gate Field Effect Transistor (FET) technology, commonly referred to as CMOS. Normally, each generation of CMOS technology is identified by its minimum feature size, e.g. half micron CMOS or quarter micron CMOS . Reducing the minimum feature size is the usual approach to making CMOS chips faster and denser simultaneo...

AI Technical Summary

Problems solved by technology

However, reducing feature size alone may lead to problems that require other, non-geometric solutions, such as enhanced circuit wiring layers.

Unfortunately, these additional features increase SRAM cell size and write time.

's vertical FETs have substantial gate-drain and gate-source overlap with its associated overlap capacitance, which may be undesirable.

This overlap capacitance is part of circuit load capacitance and contributes to other performance problems, such as Miller Effects.

Furthermore, as feature size shrinks, wiring resistance (i.e., per unit line resistance) increases, increasing RC propagation delays, which offsets some performance gains.

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