Term addressable memory of an accelerator system and method

Abstract

An improved term addressable memory of an accelerator system and method includes a mechanism for performing predetermined plurality of pattern matches of packets to classify them for use with stateful protocol processing units that can resolve session data spread across multiple data packets and process them for the ultimate destination. The invention replaces a conventional content addressable memory with a term addressable memory, whereby redundant terms are recorded with a single memory entry. Two classes of terms are used to match packet addresses and application ports, as well as a much smaller session CAM that matches the aggregate match of all terms to a specific session.

Description

SCOPE OF THE INVENTION[0001] In the above-identified application, there is described and claimed a network accelerator and method for TCP / IP that includes programmable logic for performing network protocol processing at network signaling rates. The programmable logic is configured in a parallel pipelined a architecture controlled by state machines and implements processing for predictable patterns of the majority of transmissions. In more detail, incoming packets are compared with patterns corresponding to classes of transmissions which are stored in a content addressable memory and are simultaneously stored in a dual port, dual bank application memory. The patterns are used to determine sessions to which an incoming IP datagram belongs, and data packets stored in the application memory are processed by the programmable logic. Processing of packet headers is performed in parallel and during memory transfer without the necessity of conventional store and forward techniques resulting ...

AI Technical Summary

Benefits of technology

[0002] It has now been discovered that the above-described and claimed accelerator and method has surprising improvement using an improved content or term adressable memory called "VxCAM or VIRTUAL EXTENSIBLE CONTENT ADDRESSABLE MEMORY". In accordance with the invention, VxCAM matches the minimum number of predetermined plurality of patterns resulting in fewer memory elements so that the invention can be easily implemented on-chip, narrows path width and reduces connection establishment overhead.

Problems solved by technology

If this data protocol handling must be handled in software, then there are fundamental issues in logic and software design that will always make the ability of a processor to process the packets slower than the physical ability of the network to transmit packets.

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