Apparatus for reducing power supply noise in an integrated circuit

Abstract

A main power supply continuously provides a current to a power input terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases during state changes in synchronous logic circuits implemented within the DUT. To limit variation (noise) in voltage at the power input terminal arising from these temporary increases in current demand, a charged capacitor is connected to the power input terminal during each DUT state change. The capacitor discharges into the power input terminal to supply additional current to meet the DUT's increased demand. Following each DUT state change the capacitor is disconnected from the power input terminal and charged to a level sufficient to meet a predicted increase in current demand during a next DUT state change.

Description

[0001] 1. Field of the Invention[0002] The present invention relates in general to systems for testing integrated circuits and in particular to an apparatus for reducing power supply noise in an integrated circuit under test resulting from state transitions of the logic it implements.[0003] 2. Description of Related Art[0004] An integrated circuit (IC) tester can concurrently test a set of ICs in the form of die on a silicon wafer. FIG. 1 is a block diagram illustrating a typical IC tester 10 connected through a probe card 12 to a set of similar IC devices under test (DUTs) 14. Tester 10 uses pogo pins 15 or other means to connect various input and output terminals to a set of contacts 16 on probe card 12. Probe card 12 includes a set of probes 18 for contacting input / output (I / O) pads 19 on the surface of each DUT 14 and provides conductive paths 20 linking contacts 16 to probes 18. The paths through probe card 12 allow tester 10 to transmit test signals to DUT 14 and to monitor ou...

AI Technical Summary

Benefits of technology

[0013] In accordance with one aspect of the invention, a charging current is supplied to the DUT's power input terminal from an auxiliary power supply source after each clock signal pulse to supplement a current continuously supplied by a main power supply during the test. The additional charging current reduces the need for the main power supply to increase its output current to meet the DUT's increased demand. With the output current of the main power supply being held substantially constant despite the DUT's increased demand for current, any voltage drop across path impedance between the main power supply and the DUT remains substantially constant. Thus the supply voltage at the DUT's power input terminal remains substantially constant.

[0015] In accordance with a further aspect of the invention, in a preferred embodiment thereof, the auxiliary power source includes a capacitor, a transistor switch and a voltage source. The voltage source charges the capacitor before each clock signal pulse and the switch temporarily connects the capacitor to the DUT's power input terminal at the start of each clock cycle so that the capacitor can deliver its charge to the DUT to provide the DUT's required transient charging current. The voltage to which the capacitor is charged is adjusted prior to the start of each clock signal cycle so that the capacitor delivers the amount of charge the DUT is predicted to require during the next state change. The system can regulate the DUT's supply voltage even when there is significant path impedance between the capacitor and the DUT. Thus the capacitor may be mounted on a probe card relatively distant from DUT.

Problems solved by technology

However there are practical limits to the amount by which we can reduce that reactance.

Unfortunately it is not always convenient or possible to mount a large capacitor on a probe card 12 near the power supply input terminal 26 of each DUT 14. FIG. 4 is a simplified plan view of a typical probe card 12.

However when a wafer includes a large number of ICs to be tested or an IC having a large number of densely packed terminals, there is not enough space to mount the required number of capacitors C1 of sufficient size sufficiently close to central area 27.

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