Multilayer laser trim interconnect method

Abstract

A method for creating electrical interconnects between a semiconductor die and package. In the preferred embodiment, an insulating material is applied over the die and extends to the substrate contact pads, leaving a portion of each contact pad exposed. Holes are then trimmed through the insulating material, exposing at least a portion of each die bond pad. A conductive material is then applied over the die, flowing into the holes, contacting the die bond pads, and extending out to contact at least a portion of each substrate contact pad. In another preferred embodiment, an electrically conductive bump may be formed on each die bond pad, protruding through said non-conductive material and at least partially through said conductive material. The conductive layer is then laser trimmed, forming conductive patches that serve as electrical interconnects between the die and package substrate.

Description

[0001] Not applicable.[0002] Not applicable.[0003] 1. Field of the Invention[0004] The present invention generally relates to a method for semiconductor packaging and assembly, and in particular to a method for creating improved interconnections between a die and package substrate. Still more particularly, the invention relates to a method for creating interconnects with subsequent layers of insulating and conductive materials.[0005] 2. Background Information[0006] Modern-day semiconductor devices, commonly called microchips, or "die," are fabricated on wafers, and the wafers are then sawn into grids, separating the individual chips prior to assembly in a package. Chips are fabricated in a variety of sizes, but typically range from only a few millimeters to a couple of centimeters or more in width. Each chip has numerous electrical signals. Processors, for example, may have several hundred signals. Provisions must be made to electrically connect a die to the component with which it ...

AI Technical Summary

Benefits of technology

[0047] As shown in FIG. 10A, a die 10 is attached to a package substrate 84. One or more bond pads 12 are formed on the upper surface of die 10 at or near the periphery of the die. The bond pads 12 are formed of a conductive material in accordance with known techniques and may serve as electrical points of contact for connecting die 10 to the package substrate. The upper surface of the substrate 84 includes one or more contact pads 100 formed thereon, generally by exposing an underlying metal layer by known assembly techniques. Electrical interconnects are created between the die's bond pads 12 and the contact pads 100 of a package substrate 84 without using conventional wirebonds, and thus, avoiding the problems noted above associated with wirebonds. In a preferred embodiment of the present invention, conductive "bumps" 102, preferably made of metal, are also formed on bond pads 12 on the die periphery. The bumps 102 are electrically connected to circuits in the die and may alternately serve as the electrical points of contact on die 10 in accordance with a preferred embodiment of the present invention.

[0065] The laser trim interconnect method is a semiconductor packaging method that diminishes many of the assembly, performance and reliability issues associated with existing interconnect methods while permitting the possibility of more aggressive assembly options, greater thermal and electrical performance and space conservation than conventional wirebonding and permitting a widely applicable interconnect method.

Problems solved by technology

As semiconductor devices increase in complexity and shrink in size, packaging them is becoming more and more challenging as a greater numbers of electrical signals and other connections, such as grounds, have to be routed from increasingly smaller chips.

Several issues exist with peripherally leaded packages.

For instance, as all the signals on the die must be routed out the edge of the package, as pin count increases, the footprint of the package may be undesirably forced to increase geometrically since the package area is not utilized for interconnects.

For this reason, small increases in the pin count of the die can cause relatively large increases in overall package area, since exceeding the number of pins in one package size would force the die into the next larger package family.

Further, a myriad of issues exists with wirebonding, the default interconnect method used with leadframe packages.

For a fine-pitch die, or a die that requires a wire pitch smaller than current high-volume industry standards, and thus, requires a special wirebonder and thinner wires 32, the issue of wire sweep becomes even more troublesome.

Wire sag is also an issue with relatively long or thin wires, which have an inherent sag under their own weight due to their extremely small cross-sections.

For small products, such as cell phones or other popular mobile devices, any added semiconductor package height is undesired.

While area array packaging has met many packaging challenges, the practice of wirebonding still limits the capabilities and features of a packaged device.

However, the flipchip process is technically intricate and comparatively expensive, since the bump array on the substrate surface must exactly match that of the die.

Also, there is little wiring flexibility, and bumps are difficult to apply to fine-pitch die.

These custom, exclusive-use substrates often do not achieve the manufacturing volumes of more generic packaging means, and consequently can be much more expensive.

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