Semiconductor memory device
a semiconductor and memory device technology, applied in static storage, digital storage, instruments, etc., can solve the problems of increasing load, not affecting normal read operation, and affecting the normal operation of conventional semiconductor memory devices
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first embodiment
[0050]FIG. 1 shows a semiconductor memory device according to a first preferred embodiment of the present invention.
[0051] The semiconductor memory device has a drain voltage generator 10A which differs from the drain voltage generator 10 shown in FIG. 2.
[0052] This semiconductor memory device is a non-volatile semiconductor memory capable of an electrical writing. The semiconductor memory also has a plurality of memory cell arrays MAk (k=0 to p) for storing data therein. Each memory array MAk has the same configuration, and, for example, as shown in a memory array MA0, it has a plurality of word lines WLi (I=0 to m), which are arranged in parallel with one another, and a plurality of drain lines DLj (=0 to n) which are arranged to intersect the word lines WLi. Further, a plurality of source lines SLj are arranged in parallel with one another between each of the drain lines DLj and DLj +1.
[0053] Memory cells MCEi, j at the even numbered side are connected to the word lines WLi, d...
second embodiment
[0074]FIG. 3 is a circuit diagram of a drain voltage generator according to a second embodiment of the invention. A drain voltage generator 10B is provided in place of the drain voltage generator 10 shown in FIG. 2, and the common components which are common to those in FIG. 2 are depicted by common reference numerals.
[0075] The drain voltage generator 10B provides an NMOS19, a PMOS20, and a pulse generator 21 in the drain voltage generator 10 in FIG. 2. A source of the NMOS19 is connected to a node N1, and a drain thereof is connected to the power supply voltage VCC via the PMOS20. The pulse generator 21 generates a pulse signal PLS, which goes “H” for a definite period of time, at the falling of a chip selection signal / CE, and the pulse signal PLS is supplied to a gate of the NMOS19. A gate of the PMOS20 is connected to the ground voltage GND. Other configurations of the components are the same as those of the drain voltage generator 10 shown in FIG. 2.
[0076]FIG. 4 shows signal...
third embodiment
[0082]FIG. 5 is a circuit diagram of a drain voltage generator according to a third embodiment of the invention. A drain voltage generator 10C is provided in place of the drain voltage generator 10 shown in FIG. 2, and the components which are common to those in FIG. 2 are depicted by common reference numerals.
[0083] The drain voltage generator 10C has NMOSs 22, 23 which are serially connected to each other instead of the NMOS13 of the drain voltage generator 10 in FIG. 2, and also a pulse generator 21 for controlling the NMOS23, and an inverter24. A drain and a gate of the NMOS22 are connected to nodes N1, N2.
[0084] Further, the pulse generator 21 generates a pulse signal PLS which goes “H” for a definite period of time at the falling of a chip selection signal / CE, and the pulse signal PLS is inverted by the inverter 24, and the thus inverted pulse signal is supplied to a gate of the NMOS23 as a pulse signal / PLS. Other configurations of the components are the same as those show...
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