Semiconductor nano-rod devices

Abstract

In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

Description

[0001] This application is a divisional of patent application Ser. No. 10 / 370,792, entitled “Semiconductor Nano-Rod Devices,” filed on Feb. 20, 2003, which application is incorporated herein by reference.TECHNICAL FIELD [0002] The present invention relates generally to methods for manufacturing semiconductor devices. In one aspect, the present invention relates to a method of forming a nano-rod structure for a channel of a field effect transistor. BACKGROUND [0003] Metal-oxide-semiconductor field effect transistor (MOSFET) technology is currently the dominant semiconductor technology used for manufacturing ultra-large scale integrated (ULSI) circuits. As the gate length of the MOSFET is scaled down into the sub-30 nm regime for improved performance and density, the source and drain increasingly interact with the channel to sometimes gain influence on the channel potential. Hence, a transistor with a short gate length often suffers from problems related to the inability of the gate t...

AI Technical Summary

Benefits of technology

"The present invention provides methods and structures for manufacturing semiconductor devices with improved performance. The methods involve patterning a semiconductor layer to form source, channel, and drain regions, and then annealing the channel region to improve its performance. The annealing can occur in a reaction chamber with specific gas or vacuum environments and at various temperatures and times. The annealing can also involve the use of specific etching chemistry. The resulting semiconductor devices have improved performance, including higher current and better stability."

Problems solved by technology

Hence, a transistor with a short gate length often suffers from problems related to the inability of the gate to substantially control the on / off states of the channel, which is often called short-channel effects.

However, for device scaling well into the sub-30 nm regime, the requirements for body-doping concentration, gate oxide thickness, and source / drain doping profiles become increasingly difficult to meet using conventional device structures based on bulk silicon substrates.

This may result in a parasitic off-state leakage.

However, this method requires a large amount of oxidation, and hence a large amount of oxide formation, to convert the rectangular channel cross-section shape to a rounded or circular channel cross-section.

Images