Semiconductor device with cobalt silicide contacts
a technology of silicide contacts and semiconductors, which is applied in the direction of semiconductor devices, electrical devices, transistors, etc., can solve the problems of linewidth-dependent sheet resistance, low thermal stability, and several limitations of tisi2, and achieve high performance, easy-to-manufacture contact, and high-performance silicides.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Benefits of technology
Problems solved by technology
Method used
Image
Examples
first embodiment
[0034] A preferred method employed by a first embodiment of the invention is depicted collectively in FIGS. 1 to 6. In FIG. 1, a cross-section of a semiconductor wafer 100 shows a conventional semiconductor device 105 formed in a lightly doped (n or p type) substrate 101, and which device typically has a doped (n or p type) polysilicon based gate electrode 110, a gate insulating film 115, dielectric (SiN) sidewall spacers 120, 121, shallow doped (n or p type) source / drain regions 130, 131 and deep doped (also n or p) source / drain regions 135, 136. Device 100 typically is also bordered by one or more isolation regions 138, consisting of various insulating films such as SiO2. The materials and manufacturing techniques used to create such starting structures are well-known in the art, so in the interests of brevity and clarity they are not reproduced here. While the present invention is preferably used with a polysilicon based gate electrode 110, and silicon-based source / drain regions ...
second embodiment
[0049] A preferred method employed by a second embodiment of the invention is depicted collectively in FIGS. 7 to 9. Unless otherwise noted, like numerals for the second embodiment are intended to refer to like structures as previously discussed in the first embodiment above.
[0050] As before with the first embodiment, a wafer 100 having dielectric surface and silicon surface is prepared. As before, wafer 100 is processed using any number of well-known techniques to remove or reduce native oxide.
[0051] As shown in FIG. 7, wafer 100 is then moved to a sputter chamber to deposit a Co—Ti layer 150 using a Co—Ti alloy target having a Ti content about 1 to 50 atomic percent (and preferably 1 to 10 percent) under an noble gas plasma environment, in this case, preferably argon.
[0052] A first anneal is performed at about 500 to 650 degree centigrade preferably in situ as seen in FIG. 8. This can be achieved by integrating a heating apparatus to the sputter chamber, such as a hot plate or ...
third embodiment
[0061] A preferred method employed by a third embodiment of the invention is depicted collectively in FIGS. 10 to 13. Unless otherwise noted, like numerals for the second embodiment are intended to refer to like structures as previously discussed in the first embodiment above.
[0062] As above, wafer 100 is subjected to any number of procedures to remove or reduce native oxide. Next, as shown in FIG. 10, the wafer is moved to a sputter chamber to deposit a first layer 150 consisting of about 5 to 15 nm of a Co—Ti alloy, using a Co—Ti alloy target including about 20 to 80 atomic percent of Ti.
[0063] Next, in FIG. 11, wafer 100 is then moved to a second sputter chamber (preferably in the same cluster tool) to deposit either a Co layer 151, or a Co—Ti alloy layer 151 having a richer (higher percentage) Co content than the first Co—Ti layer 150. Both layers 150, 151 are deposited under noble gas environment plasma. In the second deposition wafer 100 is heated to about 500 to 650 degree ...
PUM
| Property | Measurement | Unit |
|---|---|---|
| feature size | aaaaa | aaaaa |
| temperature | aaaaa | aaaaa |
| of time | aaaaa | aaaaa |
Abstract
Description
Claims
Application Information
Login to View More