Non-volatile semiconductor memory device and method of fabricating the same
a semiconductor and memory device technology, applied in the direction of semiconductor devices, electrical equipment, transistors, etc., can solve problems such as devices with impaired electrical characteristics, and achieve the effects of reducing local electric field concentration, reducing electrical field concentration, and less impaired electrical characteristics of semiconductor devices
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first embodiment
[0028] First Embodiment
[0029] Reference will first be made to FIG. 1 to describe the present semiconductor device in a first embodiment.
[0030] As shown in FIG. 1, the present semiconductor device is a semiconductor memory device including a semiconductor substrate 1 having a main surface having a device formation region surrounded by an isolation oxide film. The semiconductor device in the device formation region includes spaced, conductive impurity diffusion regions (not shown) and in a region located between conductive impurity diffusion regions has a tunnel insulation film 6a-6c overlying a main surface of semiconductor substrate 1, a floating gate electrode 7a-7c overlying the tunnel insulation film, an ONO film 8 overlying floating gate electrode 7a-7c, and a control gate electrode 9 overlying ONO film 8. The FIG. 1 semiconductor device is a non-volatile semiconductor memory device (so-called flash memory).
[0031] More specifically, as shown in FIG. 1, semiconductor substrate ...
second embodiment
[0054] Second Embodiment
[0055] With reference to FIGS. 9 and 10 the present semiconductor device in a second embodiment will be described. Note that FIG. 9 corresponds to FIG. 1.
[0056] The FIGS. 9 and 10 semiconductor device is basically similar in structure to the FIG. 1 semiconductor device, except the geometry of a boundary between isolation oxide film 5a, 5b and a device formation region of semiconductor substrate 1, i.e., the geometry of an upper portion (an edge 17) of trench 2a, 2b. Edge 17 has a geometry, as will more specifically be described hereinafter with reference to FIG. 10.
[0057] As shown in FIG. 10, isolation oxide film 5a has an end, or edge 17, defined by a curved portion 19 providing a curvature connecting together a flat portion 18 defining a main surface of semiconductor substrate 1 and a liner portion 20 defining a side surface of trench 2a. Note that liner portion 20 is a substantially linear portion of the side surface of trench 2a, as seen in a cross sect...
third embodiment
[0075] Third Embodiment
[0076] With reference to FIG. 18, the present semiconductor device in a third embodiment will be described hereinafter.
[0077] As shown in FIG. 18, the semiconductor device is a non-volatile semiconductor memory device including a memory cell region provided with floating gate electrode 7a-7c, control gate electrode 9 and the like, and a peripheral circuitry region provided with field effect transistors configured of gate electrodes 23a, 23b, gate insulation film 22a, 22b, and source / drain regions (not shown). The memory cell region has a structure similar to that of the present semiconductor device in the first embodiment shown in FIG. 1.
[0078] In the peripheral circuitry region, semiconductor substrate 1 has a main surface provided with trench 2c, 2d. Trench 2c, 2d has an internal wall surface with oxide film 3 disposed thereon. On oxide film 3 HDP-CVD oxide film 4 is disposed to fill trench 2c, 2d and also extend to a main surface of semiconductor substrat...
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