Membrane-limited selective electroplating of a conductive surface

Abstract

This invention relates to processes and apparati for selectively electroplating a metal layer or layers into recessed topographic features on a conductive surface. The processes and apparati of the invention are useful for fabricating metal circuit patterns, for example for creating copper interconnects between integrated circuit elements embedded in a thin layer of dielectric material on the surface of a semiconductor wafer.

Description

FIELD OF THE INVENTION [0001] This invention relates to processes and apparati for selectively electroplating a metal layer or layers into recessed topographic features on a conductive surface. The processes and apparati of the invention are useful for fabricating metal circuit patterns, for example for creating copper interconnects between integrated circuit elements embedded in a thin layer of dielectric material on the surface of a semiconductor wafer. BACKGROUND [0002] In the damascene process for fabricating integrated circuits, the electrical interconnections are created as patterns of lines and holes etched through a dielectric layer on the surface of the wafer. Such patterns are then filled with metallic copper, and electroplating is commonly used. An ideal deposition process would completely fill the recesses in the dielectric layer with copper to a level that is flush with the surrounding plateau surfaces and not deposit any copper on the plateau surfaces. [0003] Although ...

AI Technical Summary

Problems solved by technology

Although conventional electroplating technology can provide control over thickness and uniformity of the plated layer, no practical method has been disclosed that selectively deposits a metal layer into the holes and trenches or the recessed areas in the dielectric layer and simultaneously precludes depositing a metallic layer of comparable thickness on top of the plateaus separating the circuit features.

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