Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates

Abstract

In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.

Description

[0001] This is a Divisional application of U.S. patent application Ser. No. 10 / 135,071, filed on Apr. 20, 2002, which is herein incorporated by reference in its entirety, and assigned to a common assignee.BACKGROUND OF THE INVENTION [0002] (1) Field of the Invention [0003] The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of using an alternating aperture phase shift mask to fabricate sub 0.18 micron polysilicon gate transistors. [0004] (2) Description of the Prior Art [0005] Device shrinkage requires photolithographic enhancements to extend the capabilities of the processes. One such enhancement is the use of phase shift masks. Phase shifting masks are used when the desired feature size of an integrated circuit layer is on the same order of magnitude as the wavelength of light used in the photolithographic process. [0006] In a typical photolithographic mask, layer features, or traces, are formed on the mask in an opaque mat...

AI Technical Summary

Benefits of technology

This approach allows for the fabrication of polysilicon gate transistors with narrower line widths and improved device performance by eliminating the need for double masking, reducing manufacturing time, and enhancing alignment tolerance, while enabling smaller integrated circuit device sizes.

Problems solved by technology

As the pattern features approach the wavelength of the exposure light and the limits of the photolithographic equipment alignment and repeatability, it is increasingly difficult to successfully transfer the pattern features.

In practice, it is found that the current 248 nanometer lithographic tools cannot reliably create patterns below 0.15 microns.

However, application of AAPSM to random lines is limited and made difficult due to phase conflicts at direct boundaries between phases where no opaque line separates the phase areas.

The use of multiphase AAPSM causes problems in mask fabrication and cause space constraints.

There are three drawbacks to the process of the prior art.

This is both expensive and time consuming.

Though this is not an open circuit, the offset will cause a larger than normal gate resistance that will diminish device performance.

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