Method for fabricating semiconductor device and semiconductor device
a semiconductor and device technology, applied in the direction of semiconductor devices, electrical appliances, transistors, etc., can solve the problems of large change in threshold voltage, reduction of driving ability of transistors and the like, and the lik
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[0077] Hereinafter, examples according to the present invention will be described with reference to the accompanying drawings. In the following drawings, each component having substantially the same function is identified by the same reference numeral for the purpose of simplification.
first example
(First Example)
[0078] A first example of the present invention which relates to a semiconductor device 100 including two different gate insulating films 11 and 12 having different thicknesses will be described with reference to cross-sectional views shown in FIG. 1 and schematically illustrating respective process steps for fabricating a semiconductor device.
[0079] First, as shown in FIG. 1A, in an epitaxial wafer (a semiconductor substrate) 1 in which an epitaxial layer having a resistivity of 10-15 Ωcm and a thickness of 5 μm was formed on a silicon substrate of which the principal surface was the (100) plane and which has a p-type resistivity of 0.01-0.02 Ωcm, isolation regions 2 having a depth of 250 nm were formed using STI (shallow trench isolation) process, so that an isolation width between adjacent two of the isolation regions 2 was 200 nm. Furthennore, well formation and introduction of an impurity into an active region by ion implantation for adjusting a threshold voltag...
second example
(Second Example)
[0087] A second example of the present invention which relates to a semiconductor device 200 including a gate insulating film 32 will be described with reference to cross-sectional views shown in FIG. 2 and schematically illustrating respective process steps for fabricating a semiconductor device.
[0088] First, as shown in FIG. 2A, in an epitaxial wafer (a semiconductor substrate) 1 in which an epitaxial layer having a resistivity of 10-15 Ωcm and a thickness of 5 μm was formed on a silicon substrate of which the principal surface was the (100) plane and which has a p-type resistivity of 0.01-0.02 Ωcm, isolation regions 2 having a depth of 250 nm were formed using STI (shallow trench isolation) process, so that an isolation width between adjacent two of the isolation regions 2 was 200 nm. Furthermore, well formation and introduction of an impurity into an active region by ion implantation for adjusting a threshold voltage were performed.
[0089] Thereafter, as shown i...
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