Method and apparatus for precisely identifying effective addresses associated with hardware events

Abstract

A system and method for precisely identifying an instruction causing a performance-related event is disclosed. The instruction may be detected while in a pipeline stage of a microprocessor preceding a writeback stage and the microprocessor's architectural state may not be updated until after information identifying the instruction is captured. The instruction may be flushed from the pipeline, along with other instructions from the same thread. A hardware trap may be taken when the instruction is detected and/or when an event counter overflows or is within a given range of overflowing. A software trap handler may capture and/or log information identifying the instruction, such as one or more extended address elements, before returning control and initiating a retry of the instruction. The captured and/or logged information may be stored in an event space database usable by a data space profiler to identify performance bottlenecks in the application containing the instruction.

Description

CONTINUING APPLICATION DATA [0001] This application is a Continuation-In-Part of U.S. patent application Ser. No. 10 / 881,032 titled “Performance Instrumentation in a Fine Grain Multithreaded Multicore Processor,” filed Jun. 30, 2004, whose inventors are Gregory F. Grohoski, Paul J. Jordan, and Yue Chang, and which is herein incorporated by reference in its entirety.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates to computing systems and, more particularly, to performance monitoring and profiling of software applications. [0004] 2. Description of the Relevant Art [0005] Modern processors typically include performance monitoring logic (PML) to measure processor performance while running application code and to help identify performance bottlenecks. Two features commonly found in PML are (1) the ability to count certain processor events, such as cache misses, branch mispredictions, etc., and (2) the ability to cause a trap when a counter reache...

AI Technical Summary

Benefits of technology

[0010] A performance instrumentation mechanism is contemplated in which an indication that a particular event has occurred may be conveyed when in fact the event may not have occurred. In one embodiment, a counter is utilized to record the detection of events. The counter is initialized to a negative value and incremented in response to detecting an event which is being monitored. In response to detecting the counter has ...

Problems solved by technology

If the number of cache misses is suspiciously high, then that may point towards the cause of the reduced performance.

The further away the instruction which was executing when the trap occurred from the event-causing instruction, the more difficult it is to associate a program ...

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