Pulse-based flip-flop

Abstract

A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

Description

PRIORITY STATEMENT [0001] This application claims priority of Korean Patent Application Nos. 2003-84965, filed on Nov. 27, 2003 and 2004-18004, filed on Mar. 17, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the lnvention [0003] The present invention relates to a pulse-based flip-flop. [0004] 2. Description of the Related Art [0005] Flip-flops and latches may be used as data storage devices in integrated semiconductor circuits. A flip-flop may sample an input signal and convert the input signal into an output signal based upon an clock signal. A latch may differ from a flip-flop in its signal processing in that the latch may continuously sample an input signal and may convert the input signal into an output signal based on clock pulses that it may receive. [0006]FIG. 1 illustrates a block diagram of a conventional pulse-based flip-flop. The pulse-based flip...

AI Technical Summary

Benefits of technology

"The present invention provides a pulse-based flip-flop that includes a smaller number of gates and consumes less power and chip area compared to conventional flip-flops. The pulse generator includes a NAND gate, an output of a variable delay circuit, and a first and second inverter. The variable delay circuit receives a clock signal and an output of the NAND gate and feeds the output signal back to the NAND gate. The invention also provides a method for generating clock pulses using a NAND gate, a first inverter, and a second inverter. The technical effects of the invention include reduced power consumption, smaller chip area, and improved performance."

Problems solved by technology

However, the pulse generator 120 may have a large chip area and / or a higher power consumption than conventional latches which may be used in flip-flops because the pulse generator may be composed of more than four gates.

The high power consumption and / or large chip area may not be ideal when a pulse-based flip-flop is used in a circuit with high-speed operation and / or low power consumption.

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