Etching methods and apparatus and substrate assemblies produced therewith

Abstract

Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high-aspect-ratios can be etched.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of co-pending application Ser. No. 10 / 895,502, filed Jul. 20, 2004, which is a continuation of application Ser. No. 09 / 916,734, filed Jul. 26, 2001, now U.S. Pat. No. 6,784,111, which is a division of application Ser. No. 09 / 342,677, filed Jun. 29, 1999, now U.S. Pat. No. 6,635,335, which are incorporated herein by reference.TECHNICAL FIELD [0002] The invention pertains to methods and apparatus for etching silicon wafers or other substrate assemblies and to substrate assemblies. BACKGROUND OF THE INVENTION [0003] The fabrication of very large-scale integrated circuits requires processes that are compatible with small feature sizes (e.g., 0.25 μm). A particular problem is the etching of a silicon wafer or other substrate assembly to produce damascene layers, self-aligned contacts (SACs), or trench isolation. These features typically require etching relatively deeply into the wafer while maintaining a sm...

AI Technical Summary

Benefits of technology

This approach enables the etching of high-aspect-ratio features with aspect ratios of at least 10:1, maintaining a thin resist layer, and simplifies photolithographic processes by reducing resist consumption and maintaining precise etch profiles, thus overcoming the limitations of conventional etching methods.

Problems solved by technology

A particular problem is the etching of a silicon wafer or other substrate assembly to produce damascene layers, self-aligned contacts (SACs), or trench isolation.

While wet etching is simple and inexpensive, wet etching is generally inadequate to produce HAR features because wet etches tend to etch isotropically.

In addition, it is difficult to etch deep HAR features into a substrate assembly because the etchant does not flow freely into and out of the feature.

Unfortunately, dry etching with a plasma has significant limitations.

As a result, the total etching time is limited by the time required for the plasma etch to penetrate the photoresist.

Etching deep HAR features requires thick layers of photoresist to permit long etch times, and such thick layers complicate the photolithographic patterning process.

Patterning a feature as small as about 250 nm is very difficult in such a thick layer of photoresist.

Other factors limiting plasma etching include the difficulty of providing a selected distribution of ions (charged particles) and neutral particles at the substrate surface and at the bottom of a feature being etched.

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