Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same

Abstract

The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the invention [0002] The present invention relates generally to a recess channel transistor, and more particularly to a recess channel transistor and a method of forming the same, which can prevent deterioration of transistor characteristics due to misalignment between a recess gate and a top gate on the recess gate. [0003] 2. Description of the Prior Art [0004] Recently, as the design rule for currently developing semiconductor memory devices reduces the device sizes below sub-100 nm, it has become very difficult to secure sufficient data retention time. When the minimum feature size is reduced, doping density in a substrate must be increased. Thus, if the doping density in the substrate becomes higher, the electric field and the junction leakage must also increase. Therefore, in order to realize a target threshold voltage Vt required by a certain semiconductor memory device, a transistor having an existing planar structure faces a lim...

AI Technical Summary

Benefits of technology

[0015] Accordingly, the present invention has been developed in order to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a recess channel transistor and a method for forming the same, which can prevent characteristic of the transistor from deteriorating due to misalignment between a recess gate and a top gate which is arranged on the recess gate.

Problems solved by technology

Recently, as the design rule for currently developing semiconductor memory devices reduces the device sizes below sub-100 nm, it has become very difficult to secure sufficient data retention time.

Thus, if the doping density in the substrate becomes higher, the electric field and the junction leakage must also increase.

Therefore, in order to realize a target threshold voltage Vt required by a certain semiconductor memory device, a transistor having an existing planar structure faces a limitation in view of processing and device characteristics.

However, it is substantially difficult to control the alignment of the recess gate with the top gate.

Thus, the misalignment of the recess gate with the top gate may occur.

It causes a change in the characteristics of the transistor, which thereby fails to obtain desired cell characteristics.

As a result, it is difficult to store data in the cell.

Thus, the gate insulation layer 103 at the channel becomes thick, thereby abnormally increasing the threshold voltage so that tREF / tWR characteristics deteriorate.

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