Multi-zone carrier head for chemical mechanical polishing and CMP method thereof

Abstract

A multi-zone carrier head includes a housing; a retaining ring secured to a lower edge of the housing; a backing plate having a plurality of non-concentric pressure zones defined by a plurality of isolated apertures on the backing plate; wherein the backing plate has a wafer side and a non-wafer side, the wafer side facing a backside of a wafer during a CMP operation; and a plurality of pneumatic bladder for independently controlling pressure exerted in the respective non-concentric pressure zones on the backside of the wafer during the CMP operation.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates generally to chemical mechanical polishing of substrates and, more particularly, to a multi-zone carrier head for chemical mechanical polishing. [0003] 2. Description of the Prior Art [0004] In the process of fabricating integrated circuits, it is essential to form multi-level material layers and structures on a wafer. However, the prior formations often leave the top surface topography of an in-process wafer highly irregular. Such irregularities cause problems when forming the next layer over a previously formed integrated circuit structure. For example, when printing a photolithographic pattern having small geometries over previously formed layers, a very shallow depth of focus is required. Therefore, there is a need to periodically planarize the wafer surface. [0005] One technique for planarizing the surface of a wafer is chemical mechanical polishing (CMP). In CMP processing, a wafe...

AI Technical Summary

Benefits of technology

[0007] In one aspect, the invention is directed to a multi-zone carrier head for chemical mechanical polishing (CMP). The multi-zone carrier head includes a housing; a retaining ring secured to a lower edge of the housing; a backing plate having a plurality of non-concentric pressure zones defined by a plurality of isolated apertures on

Problems solved by technology

However, the prior formations often leave the top surface topography of an in-process wafer highly irregular.

Such irregularities cause problems when forming the next layer over a previously formed integrated circuit structure.

Conventional CMP suffers from some problems that need to be accounted for during the process integration.

In addition, it causes non-uniformity in the removal rate across patterns of different densities due to variations in the pressure distribution across the pattern.

This pattern density effect on removal rate can cause problems if there are both dense pattern and very sparse pattern on the wafer surface.

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