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Semiconductor device and method of fabricating the same

a technology of semiconductors and electrodes, applied in the direction of semiconductor devices, electrical equipment, transistors, etc., can solve the problems of difficult high-precision control of the length of the gate electrode, the inability to precisely control the difference between the length of the lower gate electrode and that of the upper gate electrode, and the notch-type structure of the gate electrod

Pending Publication Date: 2007-12-20
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The two-step gate electrode structure enables precise control of gate lengths, reduces the short channel effect, and lowers fabrication costs by simplifying processing steps, resulting in improved MISFET characteristics and miniaturization.

Problems solved by technology

However, there are some problems in the notch-type gate electrode structure.
For example, it is difficult to control the gate electrode length with high precision.
That is, the difference between the length of the lower gate electrode and that of the upper gate electrode cannot be precisely controlled.
Therefore, the MISFET with sufficient characteristics cannot be obtained in a case of the notched-type gate electrode.
Moreover, an etching rate of the gate electrode near an interface with a gate insulating layer becomes comparatively slow, and accordingly, forming the lower gate electrode with a straight shape is more difficult.
Furthermore, as the processing steps of forming the side wall mask on the side wall of the upper gate electrode becomes comparatively long, a cost of fabricating the MISFET becomes comparatively high.

Method used

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  • Semiconductor device and method of fabricating the same
  • Semiconductor device and method of fabricating the same
  • Semiconductor device and method of fabricating the same

Examples

Experimental program
Comparison scheme
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first embodiment

[0039] A silicon oxide layer (not illustrated) is formed over the silicon substrate 10 by using plasma-assisted CVD. Contact holes are opened in the silicon oxide layer. A metal interconnection is formed. Furthermore, the formation of the silicon-oxide layer, the contact holes, and the metal interconnection are carried out, as required. A multilevel interconnection can be formed. The surface of the silicon substrate 10 is covered with a protective insulating layer. Pad portions may be opened to complete the semiconductor device according to the

[0040] According to the first embodiment, the extension regions are formed by using the second gate electrode layer as a mask to separate the prescribed length from the channel region. As a result, a short channel effect on the MISFET can be suppressed.

[0041] Moreover, a silicon layer as the first gate electrode layer leads to the work function control and a silicon-metal compound as the second gate electrode layer leads to the low resistance...

second embodiment

[0069] A silicon oxide layer (not illustrated) is formed over the silicon substrate 30 by using plasma-assisted CVD. Contact holes are opened in the silicon oxide layer. A metal interconnection is formed. Furthermore, the formation of the silicon oxide layer, the contact holes, and the metal interconnection are carried out, as required. A multilevel interconnection can be formed. The surface of the silicon substrate 30 is covered with a protective insulating layer. Pad portions may be opened to complete the semiconductor device according to the

[0070] According to the second embodiment, the extension regions are formed by using the second gate electrode layer as a mask to separate the predetermined length from the channel region. As a result, a short channel effect on the MISFET can be suppressed.

[0071] Moreover, the two-step gate electrode is an effective structure. The silicon-germanium compound layer as the first gate electrode layer has a comparatively high activation ratio of t...

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Abstract

A semiconductor device and a method of fabricating the semiconductor device are described. There is provided the semiconductor device including, a semi-conductor substrate, a gate insulating layer on the semiconductor substrate, a two-step gate electrode formed on the gate insulating layer, the two-step gate electrode having a first gate electrode layer formed on the gate insulating layer and a second gate electrode layer formed on the first gate electrode layer, the gate length of the second gate electrode layer being longer than that of the first gate electrode layer, extension regions formed in the semiconductor substrate to interpose a channel region of the semiconductor substrate beneath the second gate electrode layer, and source-drain regions formed in the outside of the extension regions toward the channel region, the source-drain regions adjoining the extension regions.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application (No. 2004-272214, filed on Sep. 17, 2004), the entire contents of which are incorporated herein by reference. FIELD OF THE INVENTION [0002] The present invention relates to a semiconductor device and a method of fabricating the semiconductor device. DESCRIPTION OF THE BACKGROUND [0003] In recent years, a MIS LSI is desired to have more high performance and more high density integration. In order to realize these requirements, semiconductor technologies, such as miniaturizing a gate size of a MISFET and suppressing a lateral diffusion of impurities in a source-drain region, have been developed in accordance with a scaling rule. [0004] Decreasing the gate size of the MISFET by the miniaturization generally involves a short channel effect on MISFET characteristics by spreading a depletion region near a drain region of a silicon subst...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/80
CPCH01L21/28114H01L21/28194H01L21/82385H01L29/6659H01L29/42376H01L29/517H01L29/66545H01L21/823864
Inventor SASAKI, TOSHIYUKI
Owner KK TOSHIBA