Semiconductor Integrated Circuits With Stacked Node Contact Structures

Abstract

Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application claims priority under 35 U.S.C, § 120 from U.S. patent application Ser. No. 11 / 033,432, filed on Jan. 11, 2005, which in turn claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 2004-0002088, filed on Jan. 12, 2004, the disclosures of each of which are incorporated herein by reference as if set forth in there entireties.FIELD OF THE INVENTION [0002] The present invention relates to semiconductor integrated circuits and, more particularly, to contact structures for semiconductor integrated circuits. BACKGROUND OF THE INVENTION [0003] As is known by those of skill in the art, static random access memory (SRAM) integrated circuits may exhibit relatively low power consumption and high operating speeds as compared to dynamic random access memory (DRAM) integrated circuits. As a result, SRAM circuits are widely used to implement cache memories in computers and portable consumer electronic devices. [0004] T...

AI Technical Summary

Benefits of technology

"The present invention provides integrated circuits and static random access memory (SRAM) cells that include a first transistor and a second transistor that are formed at a semiconductor substrate. The first and second transistors have first and second impurity regions that are connected to each other through an interlayer insulating layer. The first and second transistors may overlap each other, and the second transistor may also overlap the first lower thin film transistor. The first and second transistors may be single crystalline thin film transistors. The integrated circuits and SRAM cells also include a first node plug that connects the first impurity region of the first transistor with the first impurity region of the second transistor, and a second node plug that connects the second impurity region of the second transistor with the first impurity region of the first transistor. The first and second node plugs may be metal plugs. The invention provides more efficient and reliable connections between the transistors in the integrated circuits and SRAM cells."

Problems solved by technology

However, bulk CMOS SRAM cells may exhibit low integration density and / or weak latch-up immunity as compared to TFT SRAM cells.

The electrical characteristics of these TFTs that are formed with a polysilicon body layer may not be as good as the electrical characteristics of bulk transistors formed at a single crystalline silicon substrate.

Images