Non-Volatile Memory With Linear Estimation of Initial Programming Voltage

a technology of initial programming voltage and non-volatile memory, which is applied in the field of non-volatile semiconductor memory, can solve the problems of unsuitable mobile and handheld environment, bulky disk drives, and easy mechanical failure, and achieve the effects of devices, reducing the number of devices, and improving the quality of the environmen

a technology of initial programming voltage and non-volatile memory, which is applied in the field of non-volatile semiconductor memory, can solve the problems of unsuitable mobile and handheld environment, bulky disk drives, and easy mechanical failure, and achieve the effects of devices, reducing the number of devices, and improving the quality of the environmen

US20080062770A1Active Publication Date: 2008-03-13WODEN TECH INC
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  • Non-Volatile Memory With Linear Estimation of Initial Programming Voltage
  • Non-Volatile Memory With Linear Estimation of Initial Programming Voltage
  • Non-Volatile Memory With Linear Estimation of Initial Programming Voltage

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

Memory System

[0047]FIG. 1 to FIG. 7 illustrate example memory systems in which the various aspects of the present invention may be implemented.

[0048]FIG. 1 illustrates schematically the functional blocks of a non-volatile memory chip. The memory chip 100 includes a two-dimensional array of memory cells 200, control circuitry 210, and peripheral circuits such as decoders, read / write circuits and multiplexers. The memory array 200 is addressable by word lines (see FIG. 2) via row decoders 230A and 230B and by bit lines (see FIG. 2) via column decoders 260A and 260B. The read / write circuits 270A and 270B allow a page of memory cells to be read or programmed in parallel. In a preferred embodiment, a page is constituted from a contiguous row of memory cells sharing the same word line. In another embodiment, where a row of memory cells are partitioned into multiple pages, block multiplexers 250A and 250B are provided to multiplex the read / write circuits 270A and 270B to the individual pag...

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Abstract

In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is related to the following U.S. patent applications: U.S. application Ser. No. ______, entitled “Method For Non-Volatile Memory With Reduced Erase / Write Cycling During Trimming Of Initial Programming Voltage,” by Yan Li, et al., filed concurrently herewith, on Sep. 12, 2006. U.S. application Ser. No. ______, entitled “Non-Volatile Memory With Reduced Erase / Write Cycling During Trimming Of Initial Programming Voltage,” by Yan Li, et al., filed concurrently herewith, on Sep. 12, 2006. U.S. application Ser. No. ______, entitled “Method For Non-Volatile Memory With Linear Estimation Of Initial Programming Voltage,” by Loc Tu, et al., filed concurrently herewith, on Sep. 12, 2006.FIELD OF THE INVENTION[0002]This invention relates generally to non-volatile semiconductor memory such as electrically erasable programmable read-only memory (EEPROM) and flash EEPROM, and specifically to determining optimum initial programming volta...

Claims

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Application Information

Patent Timeline
13 Mar 2008
Publication
US20080062770A1
IPC
G11C16/04; G11C7/00; G11C11/34; G11C29/00
CPC
G11C16/04; G11C16/12; G11C29/028; G11C29/02; G11C29/021; G11C16/3481
Inventors
TU, LOC; HOOK, CHARLES MOANA