Semiconductor device

Abstract

A semiconductor device including: a semiconductor layer including an element formation region including an element; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening exposing at least part of the electrode pad; and a bump in the opening and covering at least part of the element, the bump including first and second edges, the semiconductor layer having a forbidden region including: a first specific distance outward from a first line directly below the first edge, a second specific distance inward from the first line, a third specific distance outward from a second line directly below the second edge, and a fourth specific distance inward from the second line.

Description

[0001]This application is a divisional of U.S. patent application Ser. No. 11 / 478,485 filed on Jun. 29, 2006. This application claims the benefit of Japanese Patent Application No. 2005-197927, filed on Jul. 6, 2005, and Japanese Patent Application No. 2006-74732, filed on Mar. 17, 2006. The disclosures of the above applications are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]The present invention relates to a semiconductor device.[0003]In related-art technology, when disposing a semiconductor element such as a MOS transistor under a pad, the characteristics of the semiconductor element may be impaired due to stress during bonding. Therefore, the pad formation region and the semiconductor element formation region are separately provided in a semiconductor chip when viewed from the top side. However, since the semiconductor chip has been reduced in size and increased in degree of integration, disposition of the semiconductor element under a pad and a bump has be...

AI Technical Summary

Benefits of technology

"The invention provides a semiconductor device with an element formation region and an isolation region, an electrode pad, an interlayer dielectric, an electrode pad, a passivation layer, and a bump. The bump has a specific shape and position in relation to the element formation region and the semiconductor layer. The technical effect of the invention is to improve the reliability and performance of semiconductor devices."

Problems solved by technology

In related-art technology, when disposing a semiconductor element such as a MOS transistor under a pad, the characteristics of the semiconductor element may be impaired due to stress during bonding.

However, since the semiconductor chip has been reduced in size and increased in degree of integration, disposition of the semiconductor element under a pad and a bump has been in demand.

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