Integration schemes for fabricating polysilicon gate mosfet and high-k dielectric metal gate mosfet

Abstract

Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.

Description

FIELD OF THE INVENTION[0001]The present invention relates to methods of fabricating semiconductor structures, and particularly to methods of fabricating semiconductor structures having a polysilicon gate MOSFET and a high-K dielectric metal gate MOSFET on the same semiconductor substrate.BACKGROUND OF THE INVENTION[0002]Enhancement of complementary metal oxide semiconductor (CMOS) circuit requires improvement in the performance of both the p-type metal oxide semiconductor field effect transistors (PMOSFETs) and n-type metal oxide semiconductor field effect transistors (NMOSFETs). While the same material and processing steps were shared between PMOSFETs and NMOSFETs in the past, recent trends in high performance PMOSFETs and NMOSFETs show increased use of different materials and different processing steps among the two types of transistors.[0003]An example in which differences in the manufacture of the transistors are preferred is in the selection of the gate conductor material. In t...

AI Technical Summary

Benefits of technology

The present invention provides methods for manufacturing semiconductor structures with a polysilicon gate electrode and a high-K dielectric metal gate electrode on the same semiconductor substrate. The methods involve forming a first stack of a first gate dielectric layer and a first polysilicon layer directly on the substrate, followed by a second stack of a second gate dielectric layer, a metal gate layer, and a silicon-containing layer directly on the first polysilicon layer. The methods also involve optionally ion-bombarding the second dielectric layer prior to transferring the pattern into the second gate dielectric layer. The semiconductor structures formed using these methods provide improved performance and reliability.

Problems solved by technology

Since the use of a metal gate electrode with a high-K dielectric often introduces additional challenging, and oftentimes costly, processing steps, improvement of device performance through use of a metal gate electrode needs to be evaluated against the cost of the additional processes.

For example, performance of NMOSFETs may improve significantly with the use of a metal gate electrode and a high-K dielectric to justify the associated additional cost while improvement of performance of PMOSFETs may not be sufficient to justify associated incremental cost.

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