Semiconductor device and manufacturing method therefor

Abstract

A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.

Description

[0001]This application is a continuation application of U.S. application Ser. No. 11 / 108,729, filed Apr. 19, 2005, now allowed, the entirety of which is incorporated herein by reference.CROSS-REFERENCE TO RELATED APPLICATION[0002]The present application claims priority from Japanese patent application No. 2004-142506 filed on May 12, 2004, the content of which is hereby incorporated by reference into this application.BACKGROUND OF THE INVENTION[0003]The present invention relates to a semiconductor device and a manufacturing technique for the semiconductor device, and more particularly to a technology effectively applicable to a semiconductor device including HBTs (Heterojunction Bipolar Transistors) and a manufacturing technique for the semiconductor device.[0004]For example, there are semiconductor elements using III-V compound semiconductor such as gallium arsenide (GaAs). The compound semiconductor is characterized in that it is higher in mobility than silicon (Si) and half-insul...

AI Technical Summary

Benefits of technology

This configuration enables size reduction of power amplifier modules, improves heat radiation efficiency, and simplifies handling of semiconductor chips by directly conducting heat from the chip's element formation surface to the substrate, eliminating the need for thinning the chip.

Problems solved by technology

As downsizing of power amplifier modules progresses, as mentioned above, it is becoming difficult to ensure wire bond regions where a semiconductor chip and a wiring substrate are electrically connected with each other.