Strained-silicon CMOS device and method
a strain-silicon, cmos technology, applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve the problems of metal oxide semiconductor transistors beginning to reach their traditional scaling limits, mobility degradation, carrier transport properties change, etc., to enhance the performance of devices fabricated, the effect of increasing the drive curren
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Formation of Compressive or Tensile Dielectric Capping Layer Atop Biaxially Strained SGOI Substrate
[0137]In this example, a dielectric capping layer (compressive or tensile strain inducing layer) was used to enhance the drive current by introducing a uniaxial strain along the FET channel. When such a dielectric capping layer is deposited over an SGOI FET, the lattice structure was distorted in response to the combination of a biaxial tensile strain and a smaller uniaxial tensile or compressive stress. FIG. 9(a) depicts a schematic description of biaxial tension strained Si, in which the longitudinal lattice dimension (x-direction, parallel to the channel) was equal to the transverse lattice dimension (y-direction, in the same plane and perpendicular to the device channel) and the normal lattice dimension (z-direction, out of the channel plane). FIG. 9(b) depicts the lattice symmetry of the biaxial tension strained Si substrate depicted in FIG. 9(a) with a superimposed uniaxial tensi...
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