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Clock Selection for a Communications Processor having a Sleep Mode

a technology of communications processor and sleep mode, which is applied in the direction of generating/distributing signals, instruments, high-level techniques, etc., can solve problems such as power consumption inefficiency

Inactive Publication Date: 2009-12-24
REDPINE SIGNALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

One problem of power saving operations is the requirement for the SoC 110 to maintain any existing network connections, and create new connections as required, both operations which require the SoC 110 to come out of sleep mode periodically and check for any pending traffic to be received or transmitted before going back into a sleep mode, and to be able to do this in a manner which does not cause any network connections or requests to time out for failure to respond.
There are many drawbacks associated with the process of FIGS. 1A and 1B.
The latency in response from time 152 to time 154 followed by initialization until time 156 consumes additional time, during which interval the SOC has to be in a wake up mode prior to handling any actual requests, which also represents a power consumption inefficiency.

Method used

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  • Clock Selection for a Communications Processor having a Sleep Mode
  • Clock Selection for a Communications Processor having a Sleep Mode
  • Clock Selection for a Communications Processor having a Sleep Mode

Examples

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Embodiment Construction

[0022]FIG. 2A shows a wireless communications processor 200 including a wireless processor system on a chip (SOC) 208 coupled to an applications processor 202 which sends and receives data to the SOC 208 through a host interface 206. The SOC 208 integrates all of the functions of the wireless system other than the front end components 234 described in FIG. 1A, including ADC, DAC, mixers, amplifiers, and other functions required to modulate and demodulate from antenna 236 to baseband digital interface 232. The wireless processor 208 includes a host interface 216 to an internal bus 222, which bus is also coupled to peripherals 218, a DMA controller 220, processor 228, memory 230, an interface 226 to the front end 234, and a sleep state machine 224. System on a chip wireless processor 208 accepts a network clock 212 which has higher accuracy than host clock 204 or sleep clock 214. During sleep mode, the sleep clock 214 is coupled to sleep state machine 224, which may provide periodic w...

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PUM

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Abstract

A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.

Description

FIELD OF THE INVENTION[0001]The present invention relates to clock selection for communications systems having a sleep mode. In particular, the invention is directed to wireless communications systems having an accurate network clock, a low speed clock for a sleep mode, and a host clock for an operational mode.BACKGROUND OF THE INVENTION[0002]FIG. 1A shows a prior art communications system, which includes a System on a Chip (SoC) 110, typically comprising baseband processing for a wireless communications system, which is coupled to an RF Front End 112 which accepts signals from antenna 113, and performs the sequential operations of RF amplification, mixing to baseband using a local oscillator, and conversion to digital sampled signals using an analog to digital converter (ADC), and delivering these signals to the SoC 110 over interface 111. A transmit stream may be generated by SoC 110, which is provided to RF front end 112 as a baseband digital signal, which the RF front end 112 co...

Claims

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Application Information

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IPC IPC(8): H03L7/00
CPCG06F1/08G06F1/3209Y02B60/32Y02B60/1217G06F1/324Y02D10/00Y02D30/50
Inventor KALLAM, SUBBA REDDY
Owner REDPINE SIGNALS INC