Clock Selection for a Communications Processor having a Sleep Mode
a technology of communications processor and sleep mode, which is applied in the direction of generating/distributing signals, instruments, high-level techniques, etc., can solve problems such as power consumption inefficiency
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0022]FIG. 2A shows a wireless communications processor 200 including a wireless processor system on a chip (SOC) 208 coupled to an applications processor 202 which sends and receives data to the SOC 208 through a host interface 206. The SOC 208 integrates all of the functions of the wireless system other than the front end components 234 described in FIG. 1A, including ADC, DAC, mixers, amplifiers, and other functions required to modulate and demodulate from antenna 236 to baseband digital interface 232. The wireless processor 208 includes a host interface 216 to an internal bus 222, which bus is also coupled to peripherals 218, a DMA controller 220, processor 228, memory 230, an interface 226 to the front end 234, and a sleep state machine 224. System on a chip wireless processor 208 accepts a network clock 212 which has higher accuracy than host clock 204 or sleep clock 214. During sleep mode, the sleep clock 214 is coupled to sleep state machine 224, which may provide periodic w...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


