Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates

Abstract

A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap. A PMOS device includes a first gate dielectric over the first silicon cap. An NMOS device includes a second gate dielectric over the second silicon cap.

Description

[0001]This application claims the benefit of U.S. Provisional Application No. 61 / 146,202 filed on Jan. 21, 2009, entitled “Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates,” which application is hereby incorporated herein by reference.CROSS-REFERENCE TO RELATED APPLICATION[0002]This application relates to commonly-assigned U.S. patent application Ser. No. 12 / 341,674, filed Dec. 22, 2008, and entitled “N-FET with a Highly Doped Source / Drain and Strain Booster,” which application is hereby incorporated herein by reference.TECHNICAL FIELD[0003]This invention relates generally to integrated circuit devices, and more particularly to CMOS devices and methods for forming the same.BACKGROUND[0004]Germanium is a commonly known semiconductor material. The electron mobility and hole mobility of germanium are greater than that of silicon, hence making germanium an excellent material in the formation of integrated circuits. However, in the past, silicon gained more popular...

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor structure with improved performance for both PMOS and NMOS devices. The structure includes a germanium substrate with a first region and a second region, and a first silicon cap and a second silicon cap with different thicknesses. The method includes selectively growing the silicon caps, oxidizing the top layer of the first silicon cap, and selectively growing the second silicon cap. The resulting structure reduces adverse effects such as segregation and oxidation of germanium.

Problems solved by technology

The oxide of germanium, on the other hand, is soluble in water, and hence is not suitable for the formation of gate dielectrics.

This poses problems since the manufacturing processes of the MOS transistors often involve annealing temperatures of about 600° C. or above.

However, a further challenge faced by the semiconductor industry is that it is difficult to integrate PMOS devices formed on germanium layers or substrates with NMOS devices that are formed on high-electron-mobility materials.

However, these solutions face problems such as lattice mismatch between substrates and the materials grown thereon, and increased manufacturing cost due to increased process steps.

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