Raised Source/Drain Field Effect Transistor

Abstract

In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source / drain having a first length, where the first device is further coupled to a second raised source / drain having a second length, where the first device comprises a transistor, where the first raised source / drain and the second raised source / drain at least partially overly the substrate, where the second raised source / drain comprises a terminal electrical contact, where the second length is greater than the first length.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This is a continuation of U.S. patent Ser. No. 12 / 848,494, filed on Aug. 2, 2010, which is incorporated by reference in its entirety.TECHNICAL FIELD[0002]The exemplary embodiments of this invention relate generally to semiconductor structures and, more specifically, relate to field effect transistors having a raised source / drain.BACKGROUND[0003]Field effect transistors (PETs) have inherent device resistance, including parasitic resistances, which may be modeled as a resistor in series with the switch. Performance depends upon how fast the circuit can charge and discharge the capacitive load, i.e., the circuit's switching speed. Device resistances limit current supplied by a particular device and slow capacitive switching. Thus, how fast the circuit switches the particular load depends both upon device on-current (e.g., which is selected by design) and the device resistances. Thus, circuit performance is maximized by maximizing device on-c...

AI Technical Summary

Benefits of technology

"The invention relates to a semiconductor structure and a method of forming the structure. The structure includes a substrate and a plurality of devices, such as transistors, that are overlaid on the substrate. The devices are connected to each other through raised source / drain structures, which are also connected to a terminal electrical contact. The length of the raised source / drain structures is different, with one being longer than the other. The technical effect of the invention is to provide a more efficient and compact semiconductor structure that allows for the connection of multiple devices through raised source / drain structures."

Problems solved by technology

Device resistances limit current supplied by a particular device and slow capacitive switching.

Another design concern is that, as FET features have shrunk, what are collectively known as short channel effects have become more pronounced, resulting in a rapid increase of static power consumption.

Unfortunately, especially as FET features have shrunk, thinner gate insulator has resulted in increased gate leakages or gate induced leakages (e.g., gate to channel, gate to source or drain and gate induced drain leakage (GIDL)).

Unfortunately, however, forming source / drain (S / D) regions that are made from the same ultrathin silicon layer increases external resistance and, in particular, contact resistance.

Similar high resistance S / D diffusion and contact problems have been encountered in bulk silicon complementary metal oxide semiconductor (CMOS) devices with lightly doped drain (LDD) devices, where the S / D regions are maintained very shallow for lower voltage operation.

Especially for these very short devices, unless the S / D silicide is spaced away from the gate, the silicide can cause gate to channel or S / D shorts, for example.

In addition, silicide can interfere or interact with high-K gate dielectric formation and vice versa.

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