Estimating delay deterioration due to device degradation in integrated circuits

Abstract

A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. Generating an end-of-life netlist in which the at least one device characteristic of each device has been modified to reflect the estimated degradation or estimating a change in timing delay of each device directly from the estimated degradation of the at least one characteristic of each device. Performing a timing analysis using the estimated change in timing delay of each device to determine circuit path delays. The timing analysis being static or statistical.

Description

BACKGROUND[0001]1. Technical Field[0002]The present invention relates to the reliability of integrated circuits, and more particularly to a method for estimating delay deterioration in integrated circuits due to device degradation.[0003]2. Description of the Related Art[0004]Very large scale integration (VLSI) circuits are designed and manufactured using imperfect processes and numerous tests must be run to check the functionality of a VLSI circuit. Such circuits degrade with use over time due to known and predictable effects such as bias temperature instability (BTI) and hot carrier injection (HCI). As a result, manufactured VLSI circuits are more likely to fail in the field, even though they have successfully passed numerous functional and verification tests prior to shipping.[0005]The degradation of individual devices within a VLSI circuit may manifest itself as a change from nominal values established at the time production in one or more characteristics of a device. As an examp...

AI Technical Summary

Benefits of technology

The patent describes a method, system, and computer program for estimating the delay deterioration in an integrated circuit. The method involves using voltage and logic values during a simulation of the circuit to monitor the degradation of each device's characteristics, such as static or statistical changes in timing delay. By analyzing these changes, the method can determine the static to statistical circuit path delays over the lifetime of each device. The technical effects of this invention include more accurate and reliable information on the age-related behavior of integrated circuits, which can improve their design and reliability.

Problems solved by technology

Such circuits degrade with use over time due to known and predictable effects such as bias temperature instability (BTI) and hot carrier injection (HCI).

As a result, manufactured VLSI circuits are more likely to fail in the field, even though they have successfully passed numerous functional and verification tests prior to shipping.

A precise estimate of degradation in a VLSI circuit is nearly impossible due to such factors as highly complex designs, variations in manufacturing processes, multiple operating environments and approximations made during the modeling of these circuits.

As a result, excessive guardbands may be applied and good dies on which VLSI circuits may be formed are wasted.

On the other hand, an under-estimation of a device's degradation may result in not fully testing certain critical pathways within a circuit.

As a result, the eventual degradation of devices within a packaged integrated circuit may actually occur at a customer location even though the device passed functional and verification tests prior to shipping.

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