Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices

Abstract

A nanowire FET device includes a SOI wafer having a SOI layer over a BOX, and a plurality of nanowires and pads patterned in the SOI layer, wherein the nanowires are suspended over the BOX; an interfacial oxide surrounding each of the nanowires; and at least one gate stack surrounding each of the nanowires, the gate stack having (i) a conformal gate dielectric present on the interfacial oxide (ii) a conformal first gate material on the conformal gate dielectric (iii) a work function setting material on the conformal first gate material, and (iv) a second gate material on the work function setting material. A volume of the conformal first gate material and / or a volume of the work function setting material in the gate stack are / is proportional to a pitch of the nanowires.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)[0001]This application is a continuation of U.S. application Ser. No. 13 / 588,724 filed on Aug. 17, 2012, the disclosure of which is incorporated by reference herein.FIELD OF THE INVENTION[0002]The present invention relates to nanowire field-effect transistor (FET) devices, and more particularly, to techniques for gate work function engineering using a work function setting material an amount of which is provided proportional to nanowire pitch so as to enable multiple threshold voltage (Vt) devices.BACKGROUND OF THE INVENTION[0003]In current complementary metal-oxide semiconductor (CMOS) scaling, the use of undoped gate all around (GAA) nanowire devices is a highly investigated structure as a device choice for future CMOS. One key problem with undoped devices is the implementation of multiple threshold voltage (Vt) devices. One solution is to dope the nanowire FET. To do so, however, for aggressively scaled devices has serious drawbacks from r...

AI Technical Summary

Benefits of technology

This patent describes a technique for engineering the gate work function in nanowire field-effect transistor devices. The method involves depositing a work function setting material on the nanowires, which is proportional to their pitch. This material helps to adjust the threshold voltage of the transistors. The resulting nanowire FET device has improved performance and stability. The patent also provides a detailed description of the process for fabricating the device. The technical effect of this invention is to enhance the control of the threshold voltage of nanowire FET devices, which can improve their performance and stability.

Problems solved by technology

One key problem with undoped devices is the implementation of multiple threshold voltage (Vt) devices.

To do so, however, for aggressively scaled devices has serious drawbacks from random dopant fluctuation (RDF) effects and becomes extremely problematic as the nanowire diameter is scaled.

This however requires a substantial amount of process complexity.

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