Over-voltage tolerant circuit and method

Abstract

Over-voltage tolerant circuits and methods are provided. In one embodiment, the circuit includes a pull-up transistor coupled to an I / O pad, a sensing circuit coupled to the I / O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch. The selection circuit includes a first bias circuit to apply Vcc to a well and gate of the pull-up transistor, a second bias circuit to apply Vpad to the gate and the well of the pull-up transistor, and a non-overlap circuit configured to ensure the gate and the well of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Application No. 61 / 834,061, filed on Jun. 12, 2013, which is incorporated by reference herein.TECHNICAL FIELD[0002]This disclosure relates to the field of electronic circuits and more particularly to over-voltage tolerant circuits and methods.BACKGROUND[0003]There are several circumstances in which a circuit or electronic device may experience may experience voltages higher than the connected supply voltage. For example, a hot-swap is an operation to add or remove a circuit or electronic device from an already powered system, normally without disturbing the rest of the system. This may cause some I / O to connect to powered signals in the system before the device is connected to a power supply. In some applications, such as inter-integrated circuit (I2C) communication, coupling of integrated circuits (ICs) that run at different supply voltages can cause input / output (I / O) pads of the I...

AI Technical Summary

Benefits of technology

The hot-swap circuits and methods described in this patent reduce or eliminate the chance of malfunctions in electronic devices caused by power surges. This means that the risk of interruptions in communication or other damage to sensitive components is minimized, which can improve the reliability and overall performance of electronic systems.

Problems solved by technology

This may cause some I / O to connect to powered signals in the system before the device is connected to a power supply.

In some applications, such as inter-integrated circuit (I2C) communication, coupling of integrated circuits (ICs) that run at different supply voltages can cause input / output (I / O) pads of the IC or device to connect to a higher voltage than a supply voltage of the IC or device, potentially damaging the device or causing excessive loading or leakage currents in some I / O.

Such excessive current leakage through the I / O pad can adversely impact signals on the I2C bus.

During this period in which the n-well of the pull-up PMOS 102 is floating, commonly called a dead-zone, the risk of latch-up and associated device malfunction and interruption in communication is high.

When the resistance is high, the risk of latch-up is increased.

Additionally, the CMOS circuit can become vulnerable to latch up when a well of a transistor in a pull-up driver coupled to the I / O pad is left in a high resistance state for more than a brief time, which can occur as a result of the overvoltage condition.

Both of these phenomena can result in malfunction or destruction of the circuit.

One problem with conventional pull-down drivers is that when an external I2C pull-up supply (Vext) is applied to the I / O pad 204 and the device is unpowered, a gate of the pull-down transistor may not be strongly driven, so that the gate of the pull-down transistor can capacitively couple to the I / O pad.

This in turn causes I / O pad 204 loading, and hence undesired I2C bus distortion.

The latch 110 retains the hot-swap state and drives the gate of select transistor P1 to high thus also turning it OFF, with the undesirable result that node vpb_drvr is neither connected to Vcc nor to Vpad with a low resistance, causing the N-well and, indirectly, the gate of the PMOS pull-up transistor to float, resulting in the risk of latch-up of the electronic device, the consequent malfunction and possible interruption in communication on an I2C bus to which the I / O pad 104 is connected.

As noted above one problem with conventional pull-down drivers is that when an external I2C pull-up supply (Vext) is applied to the I / O pad 506 and the device is unpowered, the gate of the pull-down transistor 504 may not be strongly driven, and can capacitively couple to the I / O 506 pad through a parasitic capacitor C. As a result, a gate voltage of the pull-down transistor 504, normally held low during power-up or power-down, can rise weakly turning ON the pull-down transistor, and causing I / O pad 506 loading and I2C bus distortion.

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