Multi-threaded system for performing atomic binary translations

Abstract

A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.

Description

BACKGROUND OF THE INVENTION[0001]The present invention relates generally to multi-threaded software and, more particularly, to a system for performing an atomic operation by a thread in a multi-threaded binary translation system.[0002]Binary translation is the simulation of one (target) Instruction Set Architecture (ISA) with another (host) ISA. The performing of binary translations (target simulations) can be optionally accompanied with optimization and code instrumentation in which the host and target ISA may be the same or different architectures.[0003]When considering multi-core architectures, sequential target simulation is prohibitively slow, thereby motivating the use of parallel simulation in which multiple threads may be running target ISAs. In this regard the target hardware architecture provides hardware guaranteed atomic instructions for implementing synchronization primitives in a shared memory cache coherent multi-core environment or system. More specifically, when an ...

AI Technical Summary

Benefits of technology

The patent describes a method for improving the performance of a computer system by optimizing the execution of store instructions. The method includes a core data structure that keeps track of which pages have been modified and which pages have valid reservations. When the system is running in a fast mode, the data store is executed without modification. However, when the system is running in an accurate mode, the goal is to clear the reservation flags of all pages that have a valid reservation on the same coherency granule as the shared memory address. This is done by using a special flag in the data structure that indicates which pages have been modified. Pages with a clear flag in their data structure can be executed faster in the same manner as pages in the fast mode. However, pages that have a valid reservation but have not been modified for a while are required to clear all vCPUs that have reservation flags set and their RA values are in the store instruction address. The method also ensures that RM flags are only set if there is no new reservation address. This reduces the extra check overhead and improves the execution speed of subsequent stores on the page. Overall, the method improves the performance and efficiency of the computer system.

Problems solved by technology

When considering multi-core architectures, sequential target simulation is prohibitively slow, thereby motivating the use of parallel simulation in which multiple threads may be running target ISAs.

One challenge with the parallel simulation of atomic instructions relates to the complexity of parallel access to shared memory locations by multiple contending threads.

However, mutual exclusion software primitives have unnecessarily large performance overhead.

Hence, wait-free non-blocking algorithms are preferable over lock-free, however wait free non-blocking algorithms typically have inherent race conditions and will not work correctly for multi-core target systems.

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