Integrated circuit layout structure

Abstract

An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes at least one or more first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The invention relates to an integrated circuit layout structure, and more particularly, to an integrated circuit layout structure with standard cells differing in cell height.[0003]2. Description of the Prior Art[0004]Semiconductor integrated circuits are one of the most important hardware bases in the modern information society. A key design point of the semiconductor industry is to increase integration of integrated circuits, and therefore to use the area of integrated circuits more efficiently.[0005]Generally speaking, integrated circuits having complex functions are made up of many standard cells, each with basic functions. For example, standard cells of different kinds of logic gates, such as AND gates, OR gates, NOR gates, inverters, cells of flip-flops, adders and counters, are always used to realize complex integrated circuits. When designing an integrated circuit having specific functions, standard cells are se...

AI Technical Summary

Benefits of technology

The present invention provides an integrated circuit layout structure with standard cells that have a dual-height, which simplifies the design and manufacturing processes and improves space utilization efficiency. The standard cells of 2× cell height are high-speed devices with high driving capacity, while the standard cells of 1× cell height comply with low leakage and low power consumption requirements. Overall, the integrated circuit layout structure with dual-height standard cells meets both high-speed and low-power consumption integration requirements.

Problems solved by technology

It is found that valuable areas in the APR block with cells of multi-heights are always wasted and complexities of circuit design and manufacturing processes are both increased.

However, it is also found that in the APR blocks with cells of single-height, the high-speed APR and low power consumption APR are individually formed and extra connections are required.

Undesirably, “integration” is not achieved by such arrangement.

More severely, design for manufacturing (DFM) issue is generated by such arrangement.

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