Comparator circuits with local ramp buffering for a column-parallel single-slope ADC

Abstract

A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter comprises a comparator, an input voltage sampling switch, a sampling capacitor arranged to store a voltage which varies with an input voltage when the sampling switch is closed, and a local ramp buffer arranged to buffer a global voltage ramp applied at an input. The comparator circuit is arranged such that its output toggles when the buffered global voltage ramp exceeds the stored voltage. Both DC- and AC-coupled comparator embodiments are disclosed.

Description

GOVERNMENT LICENSE RIGHTS[0001]This invention was made with Government support under Contract DE-AC04-94AL85000 awarded by the Department of Energy. The Government has certain rights in the invention.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]This invention relates generally to comparator circuits, and more particularly to comparator circuits used in column-parallel single-slope analog-to-digital converters (ADCs).[0004]2. Description of the Related Art[0005]Image sensors generally include an array of pixels arranged in columns and rows. One common approach to reading out the voltages produced by the pixels in each column is to use column-parallel single-slope ADCs. A typical arrangement is shown in FIG. 1. A voltage from each column, Vin0, Vin1, . . . , Vinx is provided to one input of respective comparators A0, A1, . . . , Ax, each of which also receives a shared (or ‘global’) voltage ramp Vramp produced by a ramp generator 10. During each row readout period, ...

AI Technical Summary

Benefits of technology

The patent text presents comparator circuits that can be used in a column-parallel single-slope analog-to-digital converter. These circuits address issues with previous comparator circuits, such as low comparator kickback, constant capacitive load on the global voltage ramp, and a large input swing. The technical effects of these circuits include improved performance and accuracy in analog-to-digital conversion.

Problems solved by technology

However, there are several problems with this arrangement.

One issue is that the comparator's operating point at the instant when it toggles changes depending on the value of Vin.

As a result, the propagation delay through the comparator will vary with Vin, leading to ADC non-linearity.

A third issue is that the capacitive load on Vramp will vary with the ramp voltage as the operating point of the comparator changes.

A fourth issue is that when the comparator output toggles, there is charge kickback on the shared ramp that can give rise to column-to-column crosstalk effects.

However, the AC-coupled comparator circuit of FIG. 4a still suffers from several inherent problems.

Another drawback is that the permissible input swing for input voltage Vin is limited to approximately Vdd / 2, where Vdd is the circuit's supply voltage.

This would dramatically increase the load on the shared voltage ramp and corrupt it.

Images