Semiconductor device and method for fabricating the same

Abstract

A semiconductor device includes a substrate, a plurality of memory cells, a logic gate electrode and a high-voltage gate electrode. The substrate at least includes a memory area, a high-voltage area and a logic area. The memory cells are disposed in the memory area. The logic gate electrode is disposed on the logic area. The high-voltage gate electrode has a first portion and a second portion in contact with each other and stacked on the high-voltage area. The high-voltage gate electrode has a thickness substantially greater than that of the logic gate electrode.

Description

[0001]This application claims the benefit of People's Republic of China application Serial No. 201510207915.4, filed Apr. 28, 2015, the subject matter of which is incorporated herein by reference.BACKGROUND[0002]1. Technical Field[0003]The disclosure relates in generally related to a semiconductor device and the method for fabricating the same, and more particularly to a semiconductor device with memory cells, logic elements and high-voltage elements, as well as the method for fabricating the same.[0004]2. Description of the Related Art[0005]An non-volatile memory (NVM) device which is able to continually store information even when the supply of electricity is removed from the device containing NVM cells has been widespreadly adopted by bulk solid state memory applications in the art. Because the process for fabricating the NVM device offers good compatibility with the silicon integrated circuit (IC) process, the NVM device is thus usually integrated with complementary metal oxide ...

AI Technical Summary

Benefits of technology

The method enables precise control of etching processes, increases the process window, and achieves higher breakdown voltages for high-voltage transistors without the need for additional ion implantations, enhancing manufacturing efficiency and device performance.

Problems solved by technology

However, since the reticle that is merely prepared for forming the word lines of the NVM device has lower transmission rate (RT), thus it is more difficult to control the etching steps to stop at a desired etching, in comparison with the process prepared for forming the gate electrodes of the logic element and the high-voltage transistor.

As a result, problems either in over etch or otherwise in excess etch residue may occur due to lack of process window.

Furthermore, there are other problems faced by the conventional approaches.

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