Interconnection structure, fabricating method thereof, and exposure alignment system

Abstract

In some embodiments, an interconnection structure, an exposure alignment system, and a fabricating method thereof are provided. The method comprises: providing a wafer, forming a first to-be-connected member and multiple first alignment members in a first conductive layer; form a first opening and multiple second alignment members in a first mask layer, the first opening is used to define a position of a second to-be-connected member; based on reference and measurement coordinates of the first alignment members, and reference coordinates and measurement coordinates of the second alignment members, obtaining wafer coordinates for characterizing a position deviation of the wafer; obtaining adjustment compensation values according to stacking offsets of a preceding wafer; adjusting a position of the wafer; forming the interconnection structure in a first dielectric layer and a second dielectric layer to electrically interconnect the first to-be-connected member and the second to-be-connected member.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application claims the priority of Chinese patent application No. 201510746891.X, filed on Nov. 5, 2015, the entire content of which is incorporated herein by reference.TECHNICAL FIELD[0002]The present disclosure generally relates to the field of semiconductor technologies and, more particularly, relates to an interconnection structure, a method for fabricating the interconnection structure, and an exposure alignment system used for fabricating the interconnection structure.BACKGROUND[0003]With the development from integrated circuits to large scale integrated circuits, the circuit density of the integrated circuits are increasing. In order to improve the integration of devices, the semiconductor chips generally have a multi-layer semiconductor structure. Different layers of the semiconductor structure can be electrically connected by using interconnection structures.[0004]Referring to FIGS. 1 to 4, cross sectional structures of an ...

AI Technical Summary

Benefits of technology

This approach improves the alignment and performance of semiconductor devices by reducing positional deviations and overlay errors, thereby increasing manufacturing yield and device reliability.

Problems solved by technology

However, the plug va in the interconnection structure formed by using the existing fabricating method may easily deviate from the position of the first to-be-connected member ma.

Thus, a bridging or even a short-circuiting may be generated between the plug va and the device mb, thereby affecting the performance of the formed semiconductor device.

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