Stress induction in 3D device channel using elastic relaxation of high stress material

Abstract

A method for inducing stress in a device channel includes forming a stress adjustment layer on a substrate, the stress adjustment layer including an as deposited stress due to crystal lattice differences with the substrate. A device channel layer is formed on the stress adjustment layer. Cuts are etched through the device channel layer and the stress adjustment layer to release the stress adjustment layer to induce stress in the device channel layer. Source / drain regions are formed adjacent to the device channel layer.

Description

BACKGROUNDTechnical Field[0001]The present invention generally relates to semiconductor devices, and more particularly to substrates and methods for fabrication that yield a compressive strain employed for formation of semiconductor devices.Description of the Related Art[0002]As the device density increases, greater challenges for use of traditional external stressors in channel materials exist. A relaxed SiGe buffer can be used to induce tensile stress in silicon but no clear equivalent solution for compressive stress exists. SiGe layers can be very defective if above a critical thickness, implanted or subjected to a high thermal budget.[0003]Strained silicon and strained silicon-on-insulator (SOI) can provide enhanced properties for semiconductor devices. For example, p-type field effect transistors (PFETs) have improved performance when formed with a compressive strain channel, and n-type field effect transistors (NFETs) have improved performance when formed with a tensile strain...

AI Technical Summary

Benefits of technology

The present invention provides methods and semiconductor devices that induce stress in a device channel. The methods involve depositing a stress adjustment layer on a substrate, followed by the formation of a device channel layer on top of the stress adjustment layer. Cuts are then etched through the device channel layer and the stress adjustment layer to release the stress adjustment layer, which induces stress in the device channel layer. The resulting semiconductor device has an inducement of compressive stress in the device channel through stress relaxation of the stress adjustment layer, which also includes tensile stress from an as deposited stress provided from crystal lattice differences with the substrate.

Problems solved by technology

As the device density increases, greater challenges for use of traditional external stressors in channel materials exist.

A relaxed SiGe buffer can be used to induce tensile stress in silicon but no clear equivalent solution for compressive stress exists.

SiGe layers can be very defective if above a critical thickness, implanted or subjected to a high thermal budget.

Compressively strained silicon is much more difficult to achieve.

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