Dual-rail delay insensitive asynchronous logic processor with single-rail scan shift enable

Abstract

There is disclosed a self-timed processor. The self-timed processor includes combinatorial logic comprising multi-rail delay insensitive asynchronous logic (DIAL) to output one or more multi-rail data values to a multiplexer. It also includes a test pattern input to output a test pattern bit stream of multi-rail test data values to the multiplexer. The multiplexer has Boolean logic to output one or more multi-rail multiplexed values to a latch. The multiplexer also has a single rail selector input to select whether the multi-rail multiplexed values are the multi-rail data values or the multi-rail test data values.

Description

RELATED APPLICATION INFORMATION[0001]This patent claims priority from provisional patent application 62 / 526,897, filed Jun. 29, 2017, titled DUAL-RAIL NCL PROCESSOR WITH SINGLE-RAIL SCAN SHIFT ENABLE.NOTICE OF COPYRIGHTS AND TRADE DRESS[0002]A portion of the disclosure of this patent document contains material which is subject to copyright protection. This patent document may show and / or describe matter which is or may become trade dress of the owner. The copyright and trade dress owner has no objection to the facsimile reproduction by anyone of the patent disclosure as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright and trade dress rights whatsoever.BACKGROUNDField[0003]This disclosure relates to asynchronous digital logic circuits.Description of the Related Art[0004]In this patent, the term “processor” means a digital circuit that performs some function. A processor may typically, but not necessarily, execute stored instr...

AI Technical Summary

Benefits of technology

This patent describes a new type of logic circuit called dual-rail NCL processor with single-rail scan shift enable. This processor is designed to operate at the lowest possible power consumption and has the ability to shift between different clock frequencies. The patent also describes a method for designing synchronous logic circuits and the challenges in estimating the minimum required clock frequency for near-threshold operation. The patent also introduces the concept of asynchronous logic circuits and the delay insensitive asynchronous logic (DIAL) paradigm. The technical effects of this patent include improved power consumption and flexibility in clock frequency selection for synchronous processors, as well as improved performance and reliability for asynchronous logic circuits.

Problems solved by technology

The power consumption of a synchronous processor depends on the complexity of the processor (i.e. the number of gates and other functional elements), the clock rate, and the operating voltage.

As a consequence, it is difficult, if not impossible, to estimate the minimum required clock frequency for near-threshold voltage operation of synchronous logic circuits.

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