Implementing dram refresh power optimization during long idle mode

Abstract

A method, system and memory controller are provided for implementing refresh power optimization during long idle mode in a memory subsystem utilizing Dynamic Random Access Memory (DRAM). The DRAM includes DRAM cells requiring periodic refresh. A DRAM activity monitoring mechanism monitors an instruction queue and asserts a predefined mode register bit when the instruction queue is empty. Responsive to the asserted predefined mode register bit, a refresh rate is increased and a low power mode is established by reducing DRAM core power level for optimizing refresh power during the long idle mode to provide enhanced system performance.

Description

FIELD OF THE INVENTION[0001]The present invention relates generally to the data processing field, and more particularly, relates to a method, system and memory controller for implementing refresh power optimization during long idle mode in a memory subsystem utilizing Dynamic Random Access Memory (DRAM) to provide enhanced system performance.DESCRIPTION OF THE RELATED ART[0002]Today's need for main memory capacity and bandwidth are increasing with multi-core increasing a number of cores and agents. Data-intensive applications have increased demand for data with consolidation of cloud computing, graphics processing units (GPUs), and mobile devices.[0003]Main memory energy and power present a key design challenge. DRAM consumes power even when not in use from periodic refresh and approximately 40-50% energy spent in off-chip memory hierarchy. DRAM technology will not scale easily below 40-35 nm going forward. Also DRAM capacity, cost, and energy and power are hard to scale.[0004]DRAM ...

AI Technical Summary

Benefits of technology

The present invention provides a method, system, and memory controller for optimizing the refresh power of a memory subsystem using DRAM during long idle mode. The system monitors the instruction queue and asserts a predefined mode register bit when the queue is empty. In response, the memory controller sends a command to the DRAM to increase the refresh rate and establish a low power mode. This improves system performance by increasing the charge retention capability of DRAM cells at lower core supply. The invention overcomes disadvantages of prior art arrangements and provides a substantial improvement in latency and performance.

Problems solved by technology

Main memory energy and power present a key design challenge.

DRAM technology will not scale easily below 40-35 nm going forward.

Also DRAM capacity, cost, and energy and power are hard to scale.

DRAM cell capacitor charge leaks over time due to temperature, manufacturing issue requiring periodic refresh, for example, every 64 ms to restore lost charge to maintain data.

Performance degradation results with DRAM rank and bank being unavailable while refreshed and predictability impact of long pause during refresh.

During long idle mode, periodic refresh consumes significant energy, thereby impacts overall battery life expectations of portable mobile systems.

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