Method for making self-aligned post-cut sdb finfet device

Abstract

The disclosure includes forming a SiGe region on two adjacent fin structures and a SiP region on the fin structures adjacent to the SiGe region; forming SDB trenches; forming SiN plugs over the SDB trenches to make top-sealed hollow SDB trenches. The process for forming SDB trenches adds no additional cost, and the process is compatible with existing process flow. The SiN plugs are configured to seal the SDB trenches from top, such that the SDB trenches are filled with air and do not need to be thermally annealed. The advantage includes low fin loss in the annealing oxidation process and better controlled uniformity of the SDB trenches. Air in the SDB trenches reduces the parasitic capacitance of adjacent contacts, therefore and it is conducive to improving the device speed.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application claims priority to Chinese patent application No. CN 202010729632.7, filed on Jul. 27, 2020 at CNIPA, and entitled “METHOD FOR MAKING SELF-ALIGNED POST-CUT SDB FINFET DEVICE”, the disclosure of which is incorporated herein by reference in entirety.TECHNICAL FIELD[0002]The disclosure relates to the technical field of semiconductors, and in particular, to a method for making a self-aligned post-cut SDB FinFET device.BACKGROUND[0003]Logic design in a logic standard cell is created by using a standard cell. The height of the cell is a product of the number of tracks in the cell multiplied by the metal pitch of a chosen layer, here the tracks and pitch are measured by using the second metal layer (M2). FIG. 1 illustrates a schematic diagram of a 7.5 track cell. Half of the height between power and ground is located in the upper cell and the other half in the lower cell respectively.[0004]The cell width is related to the numbe...

AI Technical Summary

Benefits of technology

The method described in the patent text has the following benefits: The process for making the self-aligned post-cut SDB FinFET device is compatible with current tools and does not require any additional cost. The process includes a self-aligned etching process, which makes it easier to control and reduces fin loss during a subsequent annealing process. The use of air in the SDB trenches reduces parasitic capacitance, which improves device speed.

Problems solved by technology

If fin loss is large in an annealing process post FCVD (flowable chemical vapor deposition), the channel CD will expand, so the polysilicon gate cannot cover a SDB well, therefore affecting the subsequent SiGe (silicon germanium) and SiP (silicon phosphate) epitaxial growth.

Therefore, the key problem is how to control the fin loss in the FCVD annealing process.

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