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Oxide epitaxial isolation

a technology of epitaxial isolation and oxidized metal, which is applied in the direction of electrical equipment, semiconductor devices, semiconductor/solid-state device details, etc., can solve the problems of less than optimal breakdown voltage for isolating structures, low resistivity, and the inability to achieve the effect of forming a single-crystal epitaxial layer from deposited materials

Active Publication Date: 2009-03-17
MICRON TECH INC
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  • Application Information

AI Technical Summary

Benefits of technology

This approach enables the fabrication of non-volatile memory structures with reduced feature sizes and enhanced isolation, preventing leakage current and allowing for precise control of parasitic capacitance, thereby improving the performance and efficiency of integrated circuits.

Problems solved by technology

Diffusion processes can leave impurity concentrations that make it difficult to manage concentration profiles and can result in lower resistivities which lead to less than optimal breakdown voltages for isolating structures.
Processes that create a single-crystal epitaxial layer from deposited material are somewhat complex and involve the use of a “seed crystal” that allows an annealing process to align the crystals of the deposited material to create a single-crystal material from deposited (non-single-crystal) material.
One concern is that the method of forming the epi structure after the insulating oxide has been thermally grown and creating the active regions using epitaxial growth may result in anomalous tunneling characteristics at the epi / oxide interface.

Method used

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Embodiment Construction

[0015]In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and specific embodiments in which the invention may be practiced are shown by way of illustration. It is to be understood that other embodiments may be used and structural or logical changes may be made without departing from the scope of the present invention. The present description of the embodiments further make use of terms such as horizontal, vertical, top, bottom, up, down and words of similar import. These terms are meant to refer to orientation of the described element relative to a base substrate such as a wafer.

[0016]The terms “wafer” and “substrate” used in the following description include any structure having an exposed surface with which to form an integrated circuit (IC) structure or a micro electromechanical (MEM) structure. The term “substrate” is understood to include semiconductor wafers. The term “substrate” is also used to refer to semiconductor...

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Abstract

Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A crystal lattice of the vertical epitaxial structure is aligned with a crystal lattice of the strained substrate.

Description

TECHNICAL FIELD[0001]The field generally relates to manufacturing of integrated circuits, and in particular to forming vertical epitaxial structures for non-volatile memory cells.BACKGROUND[0002]Integrated circuits are often formed using fabrication steps that include diffusion processes. Photolithography is one method used to diffuse impurities into silicon to create regions of differing doping densities. Diffusion processes can leave impurity concentrations that make it difficult to manage concentration profiles and can result in lower resistivities which lead to less than optimal breakdown voltages for isolating structures.[0003]Epitaxial or “epi” layers have a much lower level of impurities than diffused layers. Epi layers are layers of semiconductor material having the same crystalline orientation as the host substrate on which it is grown—i.e., the epi layer is a single-crystal layer having a constant doping profile (unlike that created by diffusion or implantation) which is n...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L23/62H01L27/088H10B99/00
CPCH01L27/115H01L27/11521H01L29/42332H01L29/66825H01L29/7881H10B69/00H10B41/30
Inventor JONES, LYLE
Owner MICRON TECH INC