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Nonvolatile semiconductor memory device

a semiconductor and memory device technology, applied in semiconductor devices, digital storage, instruments, etc., can solve the problems of increasing the difficulty of passing the wires themselves through, the pitch of the wire becomes narrower, and the difficulty of passing the wires through

Active Publication Date: 2011-11-15
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This configuration reduces wire resistance and allows for more efficient passing of power supply lines, cell source lines, and cell well lines, maintaining high integration density while minimizing chip size and wire resistance.

Problems solved by technology

However, in an actual chip, the wiring layer immediately above a ground driver are covered by a wire which connects a bit line and a sense amplifier region, the wire pitch becomes more narrow with the progress of high integration and it becomes more difficult to pass the wires themselves through.
Consequently, even if the width of a wire becomes smaller due to miniaturization, it becomes more difficult to pass a cell source line, cell well line and power supply line through a wiring layer.
Furthermore, there is a tendency for a consumption current to increase with large capacity memory and high functionality and while further strengthening of a power supply line is becoming essential, in order to achieve this an increase in the width of power supply line is required which leads to an increase in the size of a chip.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0019]FIG. 1 is a planar view diagram which shows the structure of a NAND type flash memory related to the first embodiment of the present invention. In FIG. 1, a NAND type flash memory 1 is arranged with a cell array region 10 in which a plurality of memory strings (not shown in the diagram) are formed in a matrix shape, a row decoder 11A and a row decoder 11B arranged at either end in a word line direction (horizontal direction in the diagram) outside of the cell array region 10, cell source ground drivers 12A and 12B and cell well ground drivers 13A and 13B arranged between the cell array region 10 and the row decoder 11A, 11B, sense amplifier circuits (S / A) 14A, 14B and peripheral circuits 15A, 15B arranged at either end in a bit line direction outside of the cell array region 10. Furthermore, each memory string is comprised of a plurality of memory cells (not shown in the diagram) connected in series.

[0020]As is shown in FIG. 1, a plurality of power supply lines (third wires) 1...

second embodiment

[0038]In the second embodiment, an example in which the structure of the power supply line 16 used in the first embodiment explained above is changed will be explained.

[0039]FIG. 8 is a planar view diagram which shows the structure of a NAND type flash memory 30 related to the second embodiment of the present invention. In FIG. 8, the same structural elements as in the NAND type flash memory 1 shown in FIG. 1 have the same symbols and thus an explanation of this structure is omitted here. In addition, the structure within the cell array 10 in FIG. 8 is almost the same as the structure within the cell array 10 shown in FIG. 1. Therefore, the cross section structure shown in FIG. 2 to FIG. 7 is the same and an explanation is omitted here.

[0040]In the NAND type flash memory 30 shown in FIG. 8, power supply lines 16, 31 are formed without division on the layer M2 within the cell array region 10. Furthermore, at the bottom of FIG. 8, power supply pads 21, 32 for connecting with a power s...

third embodiment

[0043]In the third embodiment of the present invention, an example in which the structure of the row decoders 11A, 11B and the ground drivers 12A, 12B, 13A, 13B used in the first embodiment described above, is changed will be explained.

[0044]FIG. 9 is a planar view diagram which shows the structure of a NAND type flash memory 40 related to the third embodiment of the present invention. In FIG. 9, the same structural elements as in the NAND type flash memory 1 shown in FIG. 1 have the same symbols and thus an explanation of this structure is omitted here. In addition, the structure within the cell array 10 in FIG. 9 is almost the same as the structure within the cell array 10 shown in FIG. 1. Therefore, the cross section structure shown in FIG. 2 to FIG. 7 is the same and an explanation is omitted here.

[0045]In the NAND type flash memory 40 shown in FIG. 9, a row decoder 41, a cell well ground driver 42 and a cell source ground driver 43 are grouped and arranged on only the right sid...

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Abstract

The nonvolatile semiconductor memory device related to an embodiment of the present invention includes a cell array including a memory string, a bit line connected to the memory string, a first wire connected to a cell source line of a memory cell, a second wire connected to a cell well line of a memory cell, a third wire which supplies a power supply voltage to a circuit arranged outside of a region of the cell array, a fourth wire and a fifth wire being arranged in a row direction within the cell array region, and the first wire, the second wire and the third being formed in a layer above a layer in which the bit line within the cell array is formed, the fourth wire and the fifth wire being formed in the layer in which the bit line within the cell array region is formed.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-134093, filed on May 22, 2008, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a nonvolatile semiconductor memory device and in particular, a nonvolatile semiconductor memory device arranged with a plurality of nonvolatile semiconductor memory devices.[0004]2. Description of the Related Art[0005]There is a tendency to adopt methods for increasing the number of memory cells which are read once with the aim of improving the capabilities in addition to large capacity in a NAND type flash memory. Consequently, improvements in drive ability of a cell source line into which a large current flows or a ground driver of a cell well line for suppressing noise are being desired. In answer to such demands, methods are bein...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G11C11/34G11C5/06G11C16/04
CPCG11C5/025G11C16/0483H01L27/11519H01L27/11521H10B41/10H10B41/30
Inventor ABE, TAKUMI
Owner KIOXIA CORP